# Counters. Resources and methods for learning about these subjects (list a few here, in preparation for your research):

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1 ounters This worksheet and all related files are licensed under the reative ommons Attribution License, version 1.0. To view a copy of this license, visit or send a letter to reative ommons, 559 Nathan Abbott Way, Stanford, alifornia 94305, USA. The terms and conditions of this license allow for free copying, distribution, and/or modification of all licensed works by the general public. Resources and methods for learning about these subjects (list a few here, in preparation for your research): 1

2 uestion 1 uestions ount from zero to fifteen, in binary, keeping the bits lined up in vertical columns like this: Now, reading from top to bottom, notice the alternating patterns of 0 s and 1 s in each place (i.e. one s place, two s place, four s place, eight s place) of the four-bit binary numbers. Note how the least significant bit alternates more rapidly than the most significant bit. Draw a timing diagram showing the respective bits as waveforms, alternating between low and high states, and comment on the frequency of each of the bits. file uestion 2 Shown here is a simple two-bit binary counter circuit: LSB MSB The output of the first flip-flop constitutes the least significant bit (LSB), while the second flip-flop s output constitutes the most significant bit (MSB). Based on a timing diagram analysis of this circuit, determine whether it counts in an up sequence (00, 01, 10, 11) or a down sequence (00, 11, 10, 01). Then, determine what would have to be altered to make it count in the other direction. file

3 uestion 3 Draw the schematic diagram for a four-bit binary up counter circuit, using - flip-flops. file uestion 4 ounter circuits built by cascading the output of one flip-flop to the clock input of the next flip-flop are generally referred to as ripple counters. Explain why this is so. What happens in such a circuit that earns it the label of ripple? Is this effect potentially troublesome in circuit operation, or is it something of little or no consequence? file uestion 5 A style of counter circuit that completely circumvents the ripple effect is called the synchronous counter: 0 1 lock omplete a timing diagram for this circuit, and explain why this design of counter does not exhibit ripple on its output lines: lock 0 1 hallenge question: to really understand this type of counter circuit well, include propagation delays in your timing diagram. file uestion 6 Explain the difference between a synchronous counter and an asynchronous counter circuit. file

4 uestion 7 omplete a timing diagram for this synchronous counter circuit, and identify the direction of its binary count: 0 1 lock lock 0 1 file

5 uestion 8 omplete a timing diagram for this circuit, and determine its direction of count, and also whether it is a synchronous counter or an asynchronous counter: 0 1 lock lock 0 1 file

6 uestion 9 omplete a timing diagram for this circuit, and determine its direction of count, and also whether it is a synchronous counter or an asynchronous counter: 0 1 lock lock 0 1 file

7 uestion 10 omplete a timing diagram for this circuit, and determine its direction of count, and also whether it is a synchronous counter or an asynchronous counter: lock lock file

8 uestion 11 A student just learned how a two-bit synchronous binary counter works, and he is excited about building his own. He does so, and the circuit works perfectly. 0 1 lock After that success, student tries to expand on their success by adding more flip-flops, following the same pattern as the two original flip-flops: lock Unfortunately, this circuit didn t work. The sequence it generates is not a binary count. Determine what the counting sequence of this circuit is, and then try to figure out what modifications would be required to make it count in a proper binary sequence. file

9 uestion 12 The following circuit is a two-bit synchronous binary up/down counter: Up/Down 0 1 lock Explain what would happen if the upper AND gate s output were to become stuck in the high state regardless of its input conditions. What effect would this kind of failure have on the counter s operation? file

10 uestion 13 Synchronous counter circuits tend to confuse students. The circuit shown here is the design that most students think ought to work, but actually doesn t: lock Shown here is an up/down synchronous counter design that does work: Up/Down lock Explain why this circuit is able to function properly (counting in either direction), while the first circuit is not able to count properly at all. What do those extra gates do to make the counter circuit function as it should. Hint: to more easily compare the up/down counter to the faulty up counter initially shown, connect the Up/Down control line high, and then disregard any lines and gates that become disabled as a result. file

12 uestion 15 Supposed we used - flip-flops with asynchronous inputs (Preset and lear) to build a counter: PRE Up/Down PRE PRE PRE PRE lock LR LR LR LR LR With the asynchronous lines paralleled as such, what are we able to make the counter do now that we weren t before we had asynchronous inputs available to us? file uestion 16 Identify a single fault that would allow this synchronous counter circuit to count up on demand, but not down: Up/Down lock U 6 U 9 U 1 U 2 U 3 U 4 U 12 U 8 U 11 U 14 U 5 U 7 U 10 U 13 Explain why your proposed fault would cause the problem. file

13 uestion 17 A student builds a four-bit asynchronous up counter out of individual - flip-flops, but is dissatisfied with its performance: S S S S R R R R Although the counting sequence is proper, the circuit usually does not begin counting from 0000 at power-up. The fact that the circuit counts correctly suggests that there is nothing failed or mis-wired, so what could possibly be wrong? file uestion 18 The part number 74HT163 integrated circuit is a high-speed MOS, four-bit, synchronous binary counter. It is a pre-packaged unit, will all the necessary flip-flops and selection logic enclosed to make your design work easier than if you had to build a counter circuit from individual flip-flops. Its block diagram looks something like this (power supply terminals omitted, for simplicity): SPE PE P 0 P 1 P 2 P 3 TE P 74HT163 T MR Research the function of this integrated circuit, from manufacturers datasheets, and explain the function of each input and output terminal. file

14 uestion 19 Here is an eight-bit counter comprised of two four-bit 74HT163 synchronous binary counters cascaded together: SPE SPE P 0 P 1 P 2 P 3 P 0 P 1 P 2 P 3 PE TE 74HT163 T GND PE TE 74HT163 T GND MR P MR P Four output bits Four output bits Explain how this counter circuit works, and also determine which output bit is the LSB and which is the MSB. Now, examine this eight-bit counter comprised of the same two Is: SPE SPE P 0 P 1 P 2 P 3 P 0 P 1 P 2 P 3 PE TE 74HT163 T GND PE TE 74HT163 T GND MR P MR P Four output bits Four output bits Explain how this counter circuit works, and how its operation differs from the previous eight-bit counter circuit. file

15 uestion 20 A student wishes to cascade multiple four-bit synchronous counters together. His first effort looks like this, and it works well as an eight-bit counter: EN T EN T L TR L TR GND GND RST RST Four output bits Four output bits Encouraged by this success, the student decides to add another four-bit counter to the end to make a twelve-bit counter circuit: EN T EN T EN T L TR GND L TR GND L TR GND RST RST RST Four output bits Four output bits Four output bits Unfortunately, this arrangement does not work so well. It seems to work good for the first 241 counts (from to ), but then the last four bits begin to cycle as quickly as the first four bits, while the middle four bits remain in the 1111 state for 15 additional clock pulses. Something is definitely very wrong here! Determine what the problem is, and suggest a remedy for it. Hint: this situation is very similar to connecting more than two - flip-flops together to form a synchronous counter circuit. file

16 uestion 21 Some integrated circuit counters come equipped with multiple enable inputs. A good example of this is the 74HT163: SPE Enable inputs PE TE P P 0 P 1 P 2 P 3 74HT163 T MR In this case, as in others, the two enable inputs are not identical. Although both must be active for the counter to count, one of the enable inputs does something extra that the other one does not. This additional function is often referred to as a look-ahead carry, provided to simplify cascading of counters. Explain what look-ahead carry means in the context of digital counter circuits, and why it is a useful feature. file uestion 22 A student is trying to get a 74H192 up/down counter to function. However, it is simply not cooperating: LD Vdd (ount up) (ount down) lock A B D UP 74H192 DOWN A B D LR O BO Determine what the student is doing wrong with this 74H192, and then correct the schematic diagram. file

17 uestion 23 The following R circuit constitutes an automatic reset network for the counter. At power-up, it resets the counter to 0000, then allows it to count normally: R 1 R 2 R EN L TR T GND RST Predict how the operation of this automatic reset circuit will be affected as a result of the following faults. onsider each fault independently (i.e. one at a time, no multiple faults): Resistor R 1 fails open: Resistor R 2 fails open: Resistor R 3 fails open: apacitor 1 fails shorted: For each of these conditions, explain why the resulting effects will occur. file uestion 24 Determine the modulus (MOD) of a four-bit binary counter. Determine the modulus of two four-bit binary counters cascaded to make an eight-bit binary counter. file

18 uestion 25 onsider the following four-bit binary counter integrated circuit (I). When clocked by the square wave signal generator, it counts from 0000 to 1111 in sixteen steps and then recycles back to 0000 again in a single step: EN L TR T GND RST There are many applications, though, where we do not wish the counter circuit to count all the way up to full count (1111), but rather recycle at some lesser terminal count value. Take for instance the application of BD counting: from 0000 to 1001 and back again. Here is one way to truncate the counting sequence of a binary counter so that it becomes a BD counter: EN L TR T GND RST Explain how the NAND gate forces this counter to recycle after an output of 1001 instead of counting all the way up to (Hint: the reset function of this I is assumed to be asynchronous, meaning the counter output resets to 0000 immediately when the RST terminal goes low.) Also, show how you would modify this circuit to do the same count sequence (BD) assuming the I has a synchronous reset function, meaning the counter resets to 0000 if RST is low and the clock input sees a pulse. file

19 uestion 26 Suppose you had an astable multivibrator circuit that output a very precise 1 Hz square-wave signal, but you had an application which requires a pulse once every minute rather than once every second. nowing that there are 60 seconds in a minute, can you think of a way to use digital counters to act as a frequency divider so that every 60 multivibrator pulses equates to 1 output pulse? You don t have a divide-by-60 counter available, but you do have several divide-by-10 ( decade ) counters at your disposal. Engineer a solution using these counter units: EN P Decade TR EN P Decade TR EN T RO EN T RO L L A B D A B D LR LR Note: assume these counter Is have asynchronous resets. file uestion 27 When counters are used as frequency dividers, they are often drawn as simple boxes with one input and one output each, like this: MOD-10 MOD-6 MOD-2 MOD-5 f in f out1 f out2 f out3 f out4 alculate the four output frequencies (f out1 through f out4 ) given an input frequency of 1.5 khz: f out1 = f out2 = f out3 = f out4 = file

20 uestion 28 When counters are used as frequency dividers, they are often drawn as simple boxes with one input and one output each, like this: MOD-5 MOD-8 MOD-2 MOD-10 f in f out1 f out2 f out3 f out4 alculate the four output frequencies (f out1 through f out4 ) given an input frequency of 25 khz: f out1 = f out2 = f out3 = f out4 = file

21 uestion 29 A technician is trying to build a timer project using a set of cascaded counters, each one connected to its own 7-segment decoder and display: MOD-10 MOD-6 MOD-10 TP1 TP2 TP3 MOD-6 TP4 f in 1 Hz A B D A B D A B D A B D A B D A B D A B D A B D a b c d e f g a b c d e f g a b c d e f g a b c d e f g a a a a f g b f g b f g b f g b e d c e d c e d c e d c Seconds display Minutes display The technician was trying to troubleshoot this circuit, but left without finishing the job. You were sent to finish the work, having only been told that the timer circuit has some sort of problem. Your first step is to start the 1 Hz clock and watch the timing sequence, and after a few minutes of time you fail to notice anything out of the ordinary. Now, you could sit there for a whole hour and watch the count sequence, but that might take a long time before anything unusual appears for you to see. Devise a test procedure that will allow you to pinpoint problems at a much faster rate. file uestion 30 A student builds a four-bit asynchronous counter circuit using MOS - flip-flops. It seems to work... most of the time. Every once in a while, the count suddenly and mysteriously jumps out of sequence, to a value that is completely wrong. Even stranger than this is the fact that it seems to happen every time the student waves their hand next to the circuit. What do you suspect the problem to be? file

22 uestion 31 Determine the output pulses for this counter circuit, known as a ohnson counter, assuming that all outputs begin in the low state: D 0 D 1 D D 2 3 lk lock file

23 uestion 32 The following circuit is known as a ohnson counter: D D D D lock Describe the output of this circuit, as measured from the output of the far right flip-flop, assuming that all flip-flops power up in the reset condition. Also, explain what this modified version of the above ohnson counter circuit will do, in each of the five selector switch positions: D D D D lock Output file

24 uestion 33 This ohnson counter circuit is special. It outputs three square-wave signals, shifted 120 o from one another: Three-phase ohnson counter D D D lock A B lock A B Suppose the middle flip-flop s output fails in the high state. Plot the new output waveforms for signals A, B, and. Assume all outputs begin in the low state (except for the middle flip-flop, of course): lock A B file

25 uestion 34 Don t just sit there! Build something!! Learning to analyze digital circuits requires much study and practice. Typically, students practice by working through lots of sample problems and checking their answers against those provided by the textbook or the instructor. While this is good, there is a much better way. You will learn much more by actually building and analyzing real circuits, letting your test equipment provide the answers instead of a book or another person. For successful circuit-building exercises, follow these steps: 1. Draw the schematic diagram for the digital circuit to be analyzed. 2. arefully build this circuit on a breadboard or other convenient medium. 3. heck the accuracy of the circuit s construction, following each wire to each connection point, and verifying these elements one-by-one on the diagram. 4. Analyze the circuit, determining all output logic states for given input conditions. 5. arefully measure those logic states, to verify the accuracy of your analysis. 6. If there are any errors, carefully check your circuit s construction against the diagram, then carefully re-analyze the circuit and re-measure. Always be sure that the power supply voltage levels are within specification for the logic circuits you plan to use. If TTL, the power supply must be a 5-volt regulated supply, adjusted to a value as close to 5.0 volts D as possible. One way you can save time and reduce the possibility of error is to begin with a very simple circuit and incrementally add components to increase its complexity after each analysis, rather than building a whole new circuit for each practice problem. Another time-saving technique is to re-use the same components in a variety of different circuit configurations. This way, you won t have to measure any component s value more than once. file

26 Answer 1 Answers LSB MSB Answer 2 This counter circuit counts in the down direction. I ll let you figure out how to alter its direction of count! Answer 3 The circuit shown here is not the only valid solution! LSB MSB Follow-up question: what other configuration of - flip-flops could be used to make a four bit binary up counter? Answer 4 When these counters increment or decrement, they do so in such a way that the respective output bits change state in rapid sequence ( rippling ) rather than all at the same time. This creates false count outputs for very brief moments of time. Whether or not this constitutes a problem in a digital circuit depends on the circuit s tolerance of false counts. In many circuits, there are ways to avoid this problem without resorting to a re-design of the counter. 26

27 Answer 5 The timing diagram shown here is ideal, with no propagation delays shown: lock 0 1 However, even with propagation delays included (equal delays for each flip-flop), you should find there is still no ripple effect in the output count. Answer 6 A synchronous counter circuit s flip-flops are clocked simultaneously, while each of the asynchronous counter circuit s flip-flops is clocked by the output of the preceding flip-flop. Answer 7 This circuit counts down: lock Answer 8 This is a synchronous up counter. lock

28 Answer 9 This is an asynchronous up counter. lock 0 1 Answer 10 This is an asynchronous down counter. Answer 11 The errant count sequence is as such, with only eight unique states (there should be sixteen!): 0000, 0001, 0010, 0111, 1000, 1001, 1010, and A corrected up-counter circuit would look like this: lock Answer 12 The counter would not be able to count in the up direction. When commanded to count that direction, the LSB would toggle between 0 and 1, but the MSB would not change state. Answer 13 The extra AND gates allow higher-level bits to toggle if and only if all preceding bits are high. 28

29 Answer 14 This first solution requires some elimination of wires and one gate from the front end of the second counter... Up/Down lock lock... while this solution does only requires different AND gates (3-input instead of 2-input) on the first flip-flop stage of the second counter: Up/Down lock Up/Down lock I ll let you decide how you might wish to package your four-bit counter circuits, so as to allow easy cascading. This will be an excellent topic for classroom discussion! 29

30 Follow-up question: why isn t the following circuit an acceptable solution? Up/Down lock Up/Down lock Answer 15 Now, we are able to force the counter to zero (0000) or full count (1111) at will. Answer 16 Two possibilities are immediately apparent: inverter U 5 has a failed-low output, or flip-flop U 1 has a failed-low output. Answer 17 The flip-flops initial states at power-up are essentially random because they are subject to internal race conditions between the constituent gates. What is needed is some form of automatic reset to force all flip-flops to the reset state at power-up. Answer 18 P 0, P 1, P 2, and P 3 = parallel load data inputs 0, 1, 2, and 3 = count outputs P = lock pulse input MR = Master reset input SPE = Synchronous parallel enable input PE = Enable input TE = Enable input T = Terminal count output (sometimes called ripple carry output, or RO) Follow-up question: both the reset (MR) and preset (SPE) inputs are synchronous for this particular counter circuit. Explain the significance of this fact in regard to how we use this I. 30

32 Answer 24 Four bit counter modulus = 16. Eight bit counter modulus = 256. Follow-up question: is it possible for a four-bit counter to have a modulus equal to some value other than 16? Give an example! Answer 25 A timing diagram is probably the best way to answer this question! As for the synchronous-reset BD counter circuit, the only change necessary is a simple wire move (from output 1 to 0 ): EN L TR T GND RST

33 Answer 26 ascade two decade counters together, with a NAND gate to decode when the output is equal to 60: EN P Decade TR EN P Decade TR EN T RO EN T RO L L A B D A B D LR (outputs unused) LR (From 1 Hz source) Output (one "low" pulse every minute) Follow-up question: why can t we take the divide-by-60 pulse from the RO output of the second counter, as we could with the divide-by-10 pulse from the first counter? hallenge question: re-design this circuit so that the output is a square wave with a duty cycle of 50% ( high for 30 seconds, then low for 30 seconds), rather than a narrow pulse every 60 seconds. Answer 27 f out1 = 150 Hz f out2 = 25 Hz f out3 = 12.5 Hz f out4 = 2.5 Hz Follow-up question: if the clock frequency for this divider circuit is exactly 1.5 khz, is it possible for the divided frequencies to vary from what is predicted by the modulus values (150 Hz, 25 Hz, 12.5 Hz, and 2.5 Hz)? Explain why or why not. 33

34 Answer 28 f out1 = 5 khz f out2 = 625 Hz f out3 = Hz f out4 = Hz Follow-up question: if the clock frequency for this divider circuit is exactly 25 khz, is it possible for the divided frequencies to vary from what is predicted by the modulus values (5 khz, 625 Hz, Hz, and Hz)? Explain why or why not. Answer 29 Disconnect the 1 Hz clock pulse generator and re-connect the counter input to a square-wave signal generator of variable frequency. This will speed up the counting sequence and allow you to see what the problem is much faster! Follow-up question: suppose you did this and found no problem at all. What would you suspect next as a possible source of trouble that could cause the timer circuit to time incorrectly? Answer 30 This is a mistake I see students making all the time. The fact that the circuit is built with MOS components, and fails whenever an object comes near it, is a strong hint that the problem is related to stray static electric charges. It is an easily corrected problem, caused by the student not taking time to connect all the pins of their flip-flops properly. Answer 31 lock Follow-up question: if used as a frequency divider, what is the input:output ratio of this circuit? How difficult would it be to design a ohnson counter with a different division ratio? 34

35 Answer 32 ohnson counters provide a divide-by-n frequency reduction. The second counter circuit shown has the ability to select different values for n. Answer 33 lock A B Answer 34 Let the electrons themselves give you the answers to your own practice problems! 35

38 Notes 20 The hint in this question may give away too much, as the problem is precisely identical to the problem encountered with overly simplistic synchronous - flip-flop cascades. What new students tend to overlook is the necessity to enable successive stages only when all preceding stages are at their terminal counts. When you only have two stages (two - flip-flops or two I counters) to deal with, there is only one T output to be concerned with, and the problem never reveals itself. Be sure to give your students time and opportunity to present their solutions to this dilemma. Ask them how they arrived at their solutions, whether by textbook, prior example (with - flip-flops), or perhaps sheer brain power. Notes 21 The important lesson in this question is that synchronous counter circuits with more than two stages need to be configured in such a way that all higher-order stages are disabled with the terminal count of the lowest-order stage is inactive. This ensures a proper binary count sequence throughout the overall counter circuit s range. Your students should have been introduced to this concept when studying synchronous counter circuits made of individual - flip-flops, and it is the same concept here. Also important here is the realization that some I counters come equipped with the look-ahead feature built in, and students need to know how and why to use this feature. Notes 22 The point of this question is to have students research a datasheet to figure out the necessary conditions for making a digital I perform as it should. This is extremely important for students to get into the habit of doing, as it will save them much trouble as technicians! Notes 23 The purpose of this question is to approach the domain of circuit troubleshooting from a perspective of knowing what the fault is, rather than only knowing what the symptoms are. Although this is not necessarily a realistic perspective, it helps students build the foundational knowledge necessary to diagnose a faulted circuit from empirical data. uestions such as this should be followed (eventually) by other questions asking students to identify likely faults based on measurements. Notes 24 The real purpose of this question is to get students to find out what term modulus means, and how it relates to counter bits. Notes 25 Although both circuits achieve a BD count sequence, the synchronous-reset circuit is preferred because it completely avoids spurious ( ripple-like ) false outputs when recycling. Be sure to emphasize that the difference between an asynchronous and a synchronous reset function is internal to the I, and not something the user (you) can change. For an example of two otherwise identical counters with different reset functions, compare the 74HT161 (asynchronous) and 74HT163 (synchronous) four-bit binary counters. 38

39 Notes 26 Tell your students that counter circuits are quite often used as frequency dividers. Discuss the challenge question with them, letting them propose and discuss multiple solutions to the problem. The note in the question about the asynchronous nature of the counter reset inputs is very important, as synchronous-reset counter Is would not behave the same. Discuss this with your students, showing them how counters with synchronous reset inputs would yield a divide-by-61 ratio. Incidentally, a divide-by-60 counter circuit is precisely what we would need to arrive at a 1 Hz pulse waveform from a 60 Hz powerline frequency signal, which is a neat trick for obtaining a low-speed clock of relatively good accuracy without requiring a crystal-controlled local oscillator. (Where the mains power is 50 Hz instead of 60 Hz, you would need a divide-by-50 counter I know, I know...) If time permits, ask your students to think of how they could condition the 60Hz sine-wave (120 volt!) standard powerline voltage into a 60 Hz square-wave pulse suitable for input into such a frequency divider/counter circuit. Notes 27 The purpose of this question is to introduce students to the schematic convention of counter/dividers as simple boxes with MOD specified for each one, and to provide a bit of quantitative analysis (albeit very simple). Notes 28 The purpose of this question is to introduce students to the schematic convention of counter/dividers as simple boxes with MOD specified for each one, and to provide a bit of quantitative analysis (albeit very simple). Notes 29 onnecting a faulty circuit to a different input signal than what it normally runs at is an excellent way to explore faults. However, it should be noted that some faults may go undetected using this technique, because you have altered the circuit in the process. Notes 30 I didn t exactly reveal the source of trouble in the answer, but I gave enough hints that anyone familiar with MOS should be able to tell what it is! This truly is a problem I ve seen many times with my students! Notes 31 Discuss with your students how ohnson counters are quite different from binary-sequence counters, and how this uniqueness allows certain counting functions to be implemented much easier (using fewer gates) than other types of counter circuits. Notes 32 Strictly speaking, this circuit is a divide-by-2n counter, because the frequency division ratio is equal to twice the number of flip-flops. The final (#5) switch position is interesting, and should be discussed among you and your students. Notes 33 The purpose of this question is to approach the domain of circuit troubleshooting from a perspective of knowing what the fault is, rather than only knowing what the symptoms are. Although this is not necessarily a realistic perspective, it helps students build the foundational knowledge necessary to diagnose a faulted circuit from empirical data. uestions such as this should be followed (eventually) by other questions asking students to identify likely faults based on measurements. 39

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