EE320 CIRCUIT ANALYSIS II. DC-DC Converter: Implementation and Design Calculations

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1 1 EE320 CIRCUIT ANALYSIS II DC-DC Converter: Implementation and Design Calculations Design Goal: Today, we will add the circuitry to implement our dc-dc buck chopper. Recall from last lab that our goal was to design a buck chopper with the following specifications: V 18V, V, 12V, P,max 12W, P 2W, and f 30kHz. IN OUT ave out At peak output power, we found that I Lave,,max 1A, I L,max 1.167A, and I L,min 0.833A. These currents will be required to estimate the worst-case switching losses. In order to properly turn on and off the power FET, we will use an IR2117 high-side gate driver as shown in the circuit below. The driver supply voltage will be 12V as set by the LM317 linear adjustable voltage regulator circuit that you built and tested in Lab #10. All circuitry shown except for R Load should be configured on a proto-board. The 18V supply will be implemented using one of the bench-top power supplies and should conveniently couple to the board. The load will be implemented using 150 2W resistors that will be provided for you. The implementation should be done in small groups: this lab will have clear instructions for Person A and Person B to ensure that the work gets done. An important set of calculations is at the end. crit SW Figure 1: Overall Circuit Layout of 12W 18V/12V Buck Chopper

2 2 PERSON A: Your responsibilities are: 1. The main buck switch S 1 will be implemented with an IRFB31N20DPBF power FET. Secure its data sheet on one of the lab computers and identify which package pins correspond to the Gate, Drain, and Source From the data sheet, record the following data VDSS (drain to source breakdown voltage) I DM (pulsed drain current) R DS, ON T J 25 C V GS, TH,min TJ 25 C TJ,max R, JA no _ pcb 2. The main buck diode S 2 will be implemented with an MUR820PBF ultrafast recovery power diode. Secure its data sheet on the computer and identify which package pins correspond to the anode (A) and cathode (K) (see figure 1). Determine its rated voltage, current, and junction-to-ambient thermal resistance VRRM F( av) I R,JA

3 3 PERSON B: Your responsibilities are to assemble the parts for the driver: 1. Secure a STTH1R06RL (digikey part number ND) 600V, 1A ultrafast recovery diode in a DO-41 package data sheet so you can determine which side of the device is the anode and which is the cathode. Mark it on the image below 2. The IR2117 has a certain maximum positive output current (see datasheet). Given we have mandated a driver voltage VDR 12V, determine the closest available resistor in the power lab that will limit the driver current and record the value here. Expression Value Closest Commercial RGext _ = 3. The IRFB31N20DPBF power FET has the following gate charge characteristics:

4 4 Using the VDS 40V for worst case (ours will be 18V), determine the following quantities VMiller QGS 2 (use V GS, TH,min TJ 25 C for worst case) QGD Q (total gate charge for V 12V ) G DR Calculate the maximum allowable change in boot strap capacitor voltage, the minimum required boot strap capacitor charge, capacitor leakage current will be negligible). Show how you calculated them. V BS,max, and Q BS,min (you may assume that the Expression Value V BS,max = = Q BS,min = = 4. Establish a value for the boot-strap capacitor C BS and identify the closest available tantalum capacitor. Set the power supply decoupling capacitor, 1000 F (63V). C BY, to 5. Build the driver circuit on the proto-board

5 5 JOINT TASKS: Accomplish the following tasks together: 1. The power supply should be off and disconnected while completing these tasks 2. Insert the remaining parts into the proto-board: switch S 1, diode S 2, the 400 H wrapped inductor, and a 47 F 63V FC-series capacitor for C. NOTE: The node that connects FET source, diode cathode, and inductor is a critical junction, meaning they must be placed as closely as possible since currents will be changing very rapidly here. Stray inductance must be minimized! NOTE: The driver should be placed as close to the FET as possible to avoid unwanted parasitic effects (stray capacitance or inductance) HAVE THE INSTRUCTOR VERIFY YOUR LAYOUT: Make the following calculations: 1. Assuming the values found for R Gext, V GS, TH,min, VMiller Q GS 2, Q GD and that RDR 0, estimate the worst-case switch turn-on and turn-off times ( T SW, on and T SW, off ) 2. Given I L,max and I L,min from page 1, estimate the worst-case switching losses of the FET P FET, SW

6 6 3. Given the following curve which shows how the nominal resistance changes with junction temperature If we assume a worst-case junction temperature of 100 C, estimate the worst-case on-state resistance and then estimate the worst-case conduction losses of the FET P FET, cond 4. Given that the main diode has a forward voltage drop of VF 0.7V at maximum current and a reverse recovery charge of Qrr 40nC, estimate the diode conduction and switching losses. Add to P FET, SW the appropriate switching losses incurred by the FET due to reverse recovery.

7 7 5. Given R JA for the FET and the diode and the estimated power dissipation for each, calculate the anticipated worst-case junction temperatures for each device. Assume an ambient temperature of TA 25 C. If TJ max 150 C, can these devices be operated safely without heat sinks? 6. The main capacitor has a dissipation factor of DF=0.08 and a maximum rms ripple current capability of 405mA. If we assume a capacitor connection lead inductance of 20nH, a. Estimate the resonant frequency of this capacitor b. Can this capacitor handle the anticipated ripple current? c. Estimate the output voltage ripple due the capacitor ESR d. Estimate the output voltage ripple due to the change in charge imposed on the capacitor