Supertex inc. HV Channel High Voltage Amplifier Array HV256. Features. General Description. Applications. Typical Application Circuit

Transcription

1 32-Channel High Voltage Amplifier Array Features 32 independent high voltage amplifiers 3V operating voltage 295V output voltage 2.2V/µs typical output slew rate Adjustable output current source limit Adjustable output current sink limit Internal closed loop gain of 72V/V 2MΩ feedback impedance Layout ideal for die applications Applications MEMS (microelectromechanical systems) driver Piezoelectric transducer driver Optical crosspoint switches (using MEMS technology) General Description The Supertex is a 32-channel, high voltage, amplifier array integrated circuit. It operates on a single high voltage supply, up to 3V, and two low voltage supplies, and. The input voltage range is from to 4.96V. The internal closed loop gain is 72V/V, giving an output voltage of 295V when 4.96V is applied. Input voltages of up to 5.V can be applied, but will cause the output to saturate. The maximum output voltage swing is 5.V below the high voltage supply. The outputs can drive capacitive loads of up to 3pF. The maximum output source and sink current can be adjusted by using two external resistors. An external R SOURCE resistor controls the maximum sourcing current and an external R SINK resistor controls the maximum sinking current. The current limit is approximately 2.5V divided by the external resistor value. The setting is common for all 32 outputs. A low voltage silicon junction diode is made available to help monitor the die temperature. Typical Application Circuit Micro Processor DAC DAC DAC DAC High Voltage Op-Amp Array 2 3 x y y MEMS Array x DAC DAC 3 3 RSOURCE RSINK 3 3 AGND D783

2 Ordering Information Pin Configuration Part Number Package Option Packing FG-G -Lead MQFP 66/Tray -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value, High voltage supply 3V A, Analog low voltage positive supply 8.V D, Digital low voltage positive supply 8.V -Lead MQFP (top view) A, Analog low voltage negative supply D, Digital low voltage negative supply -7.V -7.V Logic input voltage -.5V to D V SIG, Analog input signal V to 6.V Storage temperature range -65 C to 5 C Maximum junction temperature 5 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Product Marking Top Marking FG LLLLLLLLLL YYWW CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID = Green Packaging Package may or may not include the following marks: Si or -Lead MQFP Typical Thermal Resistance Package θ ja -Lead MQFP 39 O C/W Operating Conditions Sym Parameter Min Typ Max Units Conditions High voltage positive supply 25-3 V --- Low voltage positive supply V --- Low voltage negative supply V --- I PP supply current ma = 3V, All = V No load I DD supply current ma = 6.V to 7.5V I NN supply current ma = -4.5V to -6.5V T J Operating temperature range C --- D783 2

3 Electrical Characteristics (over operating conditions, unless otherwise specified Sym Parameter Min Typ Max Units Conditions voltage swing V --- Input voltage range - 5. V --- OS Input voltage offset - - ±5 mv Input referred SR slew rate rise V/µs No load slew rate fall V/µs No load BW -3dB channel bandwidth KHz = 3V A O Open loop gain 7 - db --- A V Closed loop gain V/V --- R FB Feedback resistance from to ground MΩ --- C LOAD capacitive load - 3 pf --- I SOURCE sourcing current limiting range µa R SOURCE = 25KΩ I SINK sinking current limiting range µa R SINK = 25KΩ External resistance range for setting maximum current source KΩ --- R SINK External resistance range for setting maximum current sink KΩ --- CT DC DC channel to channel crosstalk db --- R SOURCE PSRR Power supply rejection ratio for,, db --- Temperature Diode Sym Min Typ Max Units Conditions PIV Peak inverse voltage V cathode to anode V F Forward diode drop V I F = µa, anode to cathode at T A = 25 C I F Forward diode current - - µa anode to cathode T C V F temperature coefficient mv/ C anode to cathode D783 3

4 Block Diagram BYP- BYP- BYP- RSOURCE RSINK To internal bus To internal bus To internal bus Output Current Source Limiting for all Output Current Sink Limiting for all VIN + - 7R R VIN + 7R - R VIN3 GND Anode + - 7R R 3 Cathode D783 4

5 Power Up/Down Issues External Diode Protection The device can be damaged due to improper power up / down sequence. To prevent damage, please follow the acceptable power up / down sequences, and add two external diodes as shown in the diagram on the right. The first diode is a high voltage diode across and, where the anode of the diode is connected to and the cathode of the diode is connected to. Any low current, high voltage diode, such as a N44, will be adequate. The second diode is a Schottky diode across and DGND, where the anode of the Schottky diode is connected to, and the cathode is connected to DGND. Any low current Schottky diode such as a N587 will be adequate. Acceptable Power Up Sequences The can be powered up with any of the following sequences listed below. ) 2) 3) 4) Inputs and Anode ) 2) 3) 4) Inputs and Anode ) & 2) Inputs 3) 4) Anode Acceptable Power Down Sequences The can be powered down with any of the following sequences listed below: ) Inputs and Anode 2) 3) 4) ) Inputs and Anode 2) 3) 4) ) Anode 2) 3) Inputs 4) & Recommended Power Up/Down Timing External Diode Protection Connection N44 or similar N587 or similar DGND Suggested Power Up/Down Sequence The needs all power supplies to be fully up and all channels refreshed with V SIG = V to force all high voltage outputs to V. Before that time, the high voltage outputs may have temporary voltage excursions above or below GND level depending on selected power up sequence. To minimize the excursions:. The and power supplies should be applied at the same time (or within a few nanoseconds). Suggested ramp up speed should be msec or longer and ramp down to be msec or longer. 3V V 6.5V V V -5.5V GND +/- V offset X 72 V V Level at Power Up Power Up Sequence Before Before V V 6.5V V 6.5V V V -5.5V V -5.5V V -5.5V 6.5V V D783 5

6 RSINK / RSOURCE The _BYP, _BYP, and _BYP pins are internal, high impedance current, mirror gate nodes, brought out to mantain stable opamp biasing currents in noisy power supply environments..uf/25v bypass capacitors, added from the _BYP pin to, from _BYP pin to, and from _BYP to, will force the high impedance gate nodes to follow the fluctuation of power lines. The expected voltages at the _BYP, and _BYP pins are typically.5 volts from their respectful power supply. The expected voltage at _BYP is typically 3.V below. BYP_ Cap.µF/25V Current limit BYP_ Set by RSOURCE BYP_ Cap.µF/25V BYP_ To internal biasing HVOpamp HVOpamp 3 BYP_ Set by RSINK BYP_ Cap.µF/25V Current limit Typical Characteristics 6 I SINK vs R SINK ( = 3V, = 6.5V, = 5.5V, T A = 25 O C) 6 I SOURCE vs R SOURCE ( = 3V, = 6.5V, = 5.5V, T A = 25 O C) 5 5 I SINK (µa) 4 3 I SOURCE (µa) max min R SINK (kω) max min R SOURCE (kω) D783 6

7 Typical Characteristics (cont.) Temperature Diode vs Temperature ( = 3V, = 6.5V, = 5.5V) -5 PSRR vs Frequency ( = 3V, = 6.5V, = 5.5V, T A = 25 O C) 7 - O C -4 V f (mv) 6 5 max max min min 25 O C 85 O C PSRR (db) max min k k k M Frequency (Hz) Diode Biasing Current (μa) -5 PSRR vs Frequency ( = 3V, = 6.5V, = 5.5V, T A = 25 O C) Input Offset vs and Temperature ( = 3V, = 6.5V, = 5.5V ) PSRR (db) Input Offset (mv) Offset at - O C Offset at 25 O C Offset at 85 O C (Volts) PSRR (db) K K K M Frequency (Hz) PSRR vs Frequency -5 ( = 3V, = 6.5V, = 5.5V, T A = 25 O C) k k k M Frequency (Hz) Gain Gain vs ( = 3V, = 6.5V, = 5.5V, T A = - O, +25 O, +85 O C) (Volts) D783 7

8 Pad Configuration (not drawn to scale) Anode Do Not Bond. For testing only. BYP- Do Not Bond. Leave Floating. BYP- GND GND Cathode RSINK RSOURCE BYP- 3 Do Not Bond. Leave Floating GND GND D783 8

9 Pad Coordinates Chip size: 76μm x 583μm Center of die is (,) Pad Name X (μm) Y (μm) Pad Name X (μm) Y (μm) BYP RSOURCE RSINK CATHODE ANODE BYP BYP GND GND Pad Name X (μm) Y (μm) GND GND D783 9

10 Pin Description Pin # Function Description Amplifier outputs High voltage positive supply. There are two pads NC No connect. 39 GND Digital ground. There are four pads. D783

11 Pin Description (cont.) Pin # Function Description 4 Analog low voltage negative supply. There are four pads. 4 NC No connect. 42 Analog low voltage positive supply. There are four pads. 43 GND Digital ground. There are four pads. 44 Analog low voltage negative supply. There are four pads. 45 Analog low voltage positive supply. There are four pads NC No connect Amplifier inputs D783

12 Pin Description (cont.) Pin # Function Description Amplifier inputs NC No connect. 86 GND Digital ground. There are four pads. 87 Analog low voltage positive supply. There are four pads. 88 Analog low voltage negative supply. There are four pads. 89 GND Digital ground. There are four pads. 9 NC No connect. 9 Analog low voltage positive supply. There are four pads. 92 BYP- 93 BYP- A low voltage. to nf decoupling decoupling capacitor across and BYP- is required. A low voltage. to nf decoupling decoupling capacitor across and BYP- is required. 94 Analog low voltage negative supply. There are four pads. 95 ANODE Anode side of of a low voltage silicon diode that can be used to monitor die temperature. 96 CATHODE Cathode side of of a low voltage silicon diode that can be used to monitor die temperature. 97 RSINK External resistor from RSINK to sets output current sinking limit. Current limit is approximately 2.5V divided by RSINK resistor value. 98 RSOURCE External resistor from RSOURCE to sets output current sourcing limit. Current limit is approximately 2.5V divided by RSOURCE resistor value. 99 BYP- A low voltage. to nf decoupling decoupling capacitor across and BYP- is required. High voltage positive supply. There are two pads. D783 2

13 -Lead MQFP Package Outline (FG) 2.x4.mm body, 3.5mm height (max),.65mm pitch, 3.2mm footprint D D E Note (Index Area E/4 x D/4) E e Top View b θ View B A A2 A Side View Seating Plane L L θ L2 View B Gauge Plane Seating Plane Note:. A Pin identifier must be located in the index area indicated. The Pin identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A A2 b D D E E e L L L2 θ θ MIN 2.5* * 9.8* 6.95* 3.8*.73 O 5 O Dimension NOM (mm) BSC REF BSC MAX * 2.2* 7.45* 4.2*.3 7 O 6 O JEDEC Registration MS-22, Variation GC-2, Issue B, Dec * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-MQFPFG, Version F439. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 23 All rights reserved. Unauthorized use or reproduction is prohibited. D Bordeaux Drive, Sunnyvale, CA 9489 Tel: