BJT Fixed Bias ENGI 242 ELEC 222. BJT Biasing 1

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1 BJT Fixed Bias ENGI 242 ELEC 222 BJT Biasing 1 For Fixed Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point Graphical Solution using Loadlines Computational Analysis Design and test design using a computer simulation January 2004 ENGI 242/ELEC 222 2

2 Complete CE Amplifier with Fixed Bias January 2004 ENGI 242/ELEC Fixed Bias and Equivalent DC Circuit January 2004 ENGI 242/ELEC 222 4

3 Fixed-Bias Circuit January 2004 ENGI 242/ELEC DC Equivalent Circuit January 2004 ENGI 242/ELEC 222 6

4 Base-Emitter (Input) Loop Using Kirchoff s voltage law: V CC + I B R B + V BE = 0 Solving for IB: I B = V CC - V R B BE January 2004 ENGI 242/ELEC Collector-Emitter (Output) Loop Since: IC = β IB Using Kirchoff s voltage law: VCC + IC RC + VCE = 0 Because: VCE = VC VE Since VE = 0V, then: VC = VCE And VCE =VCC -ICRC Also: VBE = VB -VE with VE = 0V, then: VB = VBE January 2004 ENGI 242/ELEC 222 8

5 BJT Saturation Regions When the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that: I Csat = where V CC - VCE R C V CE = 0.2 V January 2004 ENGI 242/ELEC Determining Icsat January 2004 ENGI 242/ELEC

6 Determining ICSAT for the fixed-bias configuration January 2004 ENGI 242/ELEC Load Line Analysis January 2004 ENGI 242/ELEC

7 Load Line Analysis The end points of the line are : I Csat and V CE cutoff For load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff I Csat : V CEcutoff : I Csat = V = V V R CC C V CE = 0V CE CC I C = 0mA Where IB intersects with the load line we have the Q point Q-point is the particular operating point: Value of R B Sets the value of I B Where I B and Load Line intersect Sets the values of V CE and I C. January 2004 ENGI 242/ELEC Circuit values effect Q-point January 2004 ENGI 242/ELEC

8 Circuit values effect Q-point (continued) January 2004 ENGI 242/ELEC Circuit values effect Q-point (continued) January 2004 ENGI 242/ELEC

9 Load-line analysis January 2004 ENGI 242/ELEC DC Fixed Bias Circuit Example January 2004 ENGI 242/ELEC

10 Loadline Example Family of Curves January 2004 ENGI 242/ELEC Emitter Stabilized Bias ENGI 242 ELEC 222

11 BJT Emitter Bias For the Emitter Stabilized Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point Graphical Solution using Loadlines Computational Analysis Design and test design using a computer simulation January 2004 ENGI 242/ELEC Improved Bias Stability The addition of RE to the Emitter circuit improves the stability of a transistor output Stability refers to a bias circuit in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor forward current gain (β) The temperature (TA or ambient temperature) surrounding the transistor circuit is not always constant Therefore, the transistor β is not a constant value January 2004 ENGI 242/ELEC

12 Emitter-Stabilized Bias Circuit Adding an emitter resistor to the circuit between the emitter lead and ground stabilizes the bias circuit over Fixed Bias January 2004 ENGI 242/ELEC Base-Emitter Loop January 2004 ENGI 242/ELEC

13 Equivalent Network January 2004 ENGI 242/ELEC Reflected Input impedance of RE January 2004 ENGI 242/ELEC

14 Base-Emitter Loop Applying Kirchoffs voltage law: -VCC + IB RB + VBE +IE RE = 0 Since: IE = (β + 1) IB We can write: -VCC + IB RB + VBE + (β + 1) IB RE = 0 Grouping terms and solving for I B : Or we could solve for IE with: I B = January 2004 ENGI 242/ELEC V CC - V BE R B + (β+1)re RB - V CC + I E + V BE + I E R E = 0 ( β + 1) Collector-Emitter Loop January 2004 ENGI 242/ELEC

15 Collector-Emitter Loop Applying Kirchoff s voltage law: -VCC + IC RC + VCE + IE RE = 0 Assuming that I E I C and solving for VCE: VCE =VCC IC (RC + RE) If we can not use IE IC the IC = αie and: VCE =VCC IC (RC + αre) Solve for V E : VE = IE RE Solve for V C : VC = VCC -IC RC or VC = VCE + IE RE Solve for V B : VB = VCC -IBRB or VB = VBE + IE RE January 2004 ENGI 242/ELEC Transistor Saturation At saturation, VCE is at a minimum We will find the value VCEsat = 0.2V For load line analysis, we use VCE = 0 To solve for ICSAT, use the output KVL equation: I CSAT = V CC - VCE R C + RE January 2004 ENGI 242/ELEC

16 Load Line Analysis The load line end points can be calculated: At cutoff: At saturation: V = V CE CC I C = 0 ma I C = V CC V CE = 0V R C + R E January 2004 ENGI 242/ELEC Emitter Stabilized Bias Circuit Example January 2004 ENGI 242/ELEC

17 Design of an Emitter Bias CE Amplifier Where.1VCC VE.2VCC And.4VCC VC.6VCC January 2004 ENGI 242/ELEC Emitter Bias with Dual Supply January 2004 ENGI 242/ELEC

18 Emitter Bias with Dual Supply Input Output January 2004 ENGI 242/ELEC