3 The TTL NAND Gate. Fig. 3.1 Multiple Input Emitter Structure of TTL

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1 3 The TTL NAND Gate 3. TTL NAND Gate Circuit Structure The circuit structure is identical to the previous TTL inverter circuit except for the multiple emitter input transistor. This is used to implement a diode switching structure in active transistor form using parallel junction diffusions for several emitters. Fig. 3. Multiple Input Emitter Structure of TTL If any input is low, the corresponding base-emitter junction becomes forward-biased and the transistor conducts. The other characteristics of the circuit and its transfer characteristic are identical to those of the inverter circuit. 3.2 Logical Operation A table of conduction states can be drawn up showing the state of each transistor in the circuit for all possible input conditions as before to verify the logic function performed. The direction of conduction of T can be in the forward or reverse mode so this should also be noted in the table. It can be seen from the table that the output goes LO only when both inputs are HI which verifies the NAND function. IN IN2 T T 2 T 3 T 4 D OUPUT LO LO ON for OFF OFF ON ON HI LO HI ON for OFF OFF ON ON HI HI LO ON for OFF OFF ON ON HI HI HI ON rev ON ON OFF OFF LO

2 V CC R 3 R 30Ω Input Input 2 R N T.6kΩ N2 T 2 N3 N4 T 4 N5 N6 N7 T 3 Output (no load) R 2 kω Fig. 3.2 Circuit Diagram of a Standard 2-input TTL NAND Gate 2

3 3.3. Circuit Analysis It is of interest to examine the conditions for the different logic states of the NAND Gate circuit, particularly with regard to estimating the power consumption in each state. This can be done by first establishing the voltages at each of the nodes N N7 in the circuit and then finding the total current drawn from the power supply. (a) At Least One Input LO Output HI To aid in the analysis, the NAND Gate circuit can be redrawn with the transistors which are non-conducting or OFF removed from the circuit as shown in Fig Then the potentials, relative to ground, can be determined for each of the nodes in turn. Under this condition, T is ON in forward mode, T 2 is OFF, T 3 is OFF, while T 4 is ON at the point of cutin and therefore T 2 and T 3 have been removed from the circuit. V CC I I I 3 R 3 R 30Ω Input Input 2 0. V R N T N2.6kΩ N4 N3 T 4 N5 N6 N7 Output (no load) R 2 kω Fig. 3.3 NAND Gate Circuit Redrawn with at least One Input LO 3

4 (i) T ON in forward mode and is operating in saturation as there is only a leakage current from T 2 available as collector current, i.e. T operates with a large base current and negligible collector current where I C MAX 0. The input logic LO voltage is taken as 0.V. Then: Node N : VN Vi + VE V (ii) With T operating in saturation, its collector-emitter voltage is V CE 0.V so that: NodeN2 : VN2 Vi + VCE V (iii) With T 4 operating at the point of cut-in its base current and hence its collector current can be taken as zero. This means that there is no voltage drop across either resistor R or R 3 and so the potential at both sides of these resistors is equal to the supply voltage V CC giving: Node N3, Node N5: VN3 VN5 VCC 5V (iv) Node N4 is pulled low by the resistor R 2 which has no current flowing through it so that: NodeN4 : V N4 0V (v) Finally, with T 4 operating at the point of cut-in: Node N6 : VN6 VN3 VE4 CUT-IN V and with the diode at cut-in also: NodeN7 : VN7 VN6 VDCUT-IN V 4

5 The current drawn from the supply can then be obtained as: I V V R 5 0.9V CC N.025mA with I and I 3 0 since negligible current flows into the base or collector of T 4 while at the point of cut-in. The power consumption of the gate with the output in the logic Hi state can then be obtained as: POH VCC x I 5V x.025ma 5.25mW (b) oth Inputs HI Output LO Under this condition T is ON in the reverse mode, T 2 is ON, T 3 is ON and T 4 is OFF. Fig. 3.4 shows the NAND gate circuit redrawn with T 4 removed. Potentials must be determined in a different order this time. V CC I I I 3 R.6kΩ R 3 30Ω N5 Input Input 2 5V 5V R N T N2 T 2 N3 N4 N6 N7 T 3 Output (no load) R 2 kω Fig. 3.4 NAND Gate Circuit Redrawn with oth Inputs HI 5

6 (i) With T 3 ON and operating in saturation: NodeN4 : VN4 VE3 0.8V (ii) With T 2 also ON and in saturation: NodeN2 : VN2 VN4 + VE V (iii) Since T is ON in the reverse mode, the base-collector voltage in this mode can be taken as the same as the base-emitter voltage of a transistor operating in the forward active mode so that: Node N: VN VN2 + VCONREV V (iv) With T 2 operating in saturation, its collector emitter voltage will be V CE 0.V so that: NodeN3 : VN3 VN4 + VCE2 sat V (v) With T 4 OFF no current will flow through resistor R 3 and consequently Node N 5 will be pulled up to the supply rail voltage: Node N5 : VN5 VCC 5V (vi) With T 3 ON and in saturation, its collector-base voltage will be at a saturation value so that the output voltage at Node N7 is simply: NodeN7: VN7 VCE3 0.V (vii) With T 4 and the diode non-conducting, the potential at Node N6 is somewhat ill-defined and depends on the resistances of the nonconducting junctions of these devices but will lie somewhere between that of Nodes N 3 and N 7, i.e. between 0. and 0.9V. However, this voltage is not significant. 6

7 The current drawn from the supply this time is given by the sum of I and I with I 3 0: Then: and I V V R 5 2.3V CC N 0.675mA I V V R 5 0.9V.6kΩ CC N3 2.56mA The power consumption when the output is LO is then given as: P OL VCC x(i + I ) 5 x ( ) 6.75mW If the NAND gate is assumed to spend half of its time in each logic state then the average power consumption can be expressed as: P P + P OH OL AVE 0.56mW 7