Common Emitter BJT Amplifier Design Current Mirror Design

Transcription

1 Common Emitter BJT Amplifier Design Current Mirror Design 1

2 Some Random Observations Conditions for stabilized voltage source biasing Emitter resistance, R E, is needed. Base voltage source will have finite resistance, R B. 1 R E needs to be much larger than R B. Small R B - relative to R S - will attenuate input signal. Larger R E permits larger R B, but results in lower gain. Gain = -R C /R E for R E >> r e. Split R E with bypassing increases gain. Requires large bypass capacitor. Limiting case - entire R E bypassed: Gain = - g m R C. Simplified rule-of-thumb biasing is adequate. 2

3 Conflicting Bias and Gain Issues Biasing If R B is small relative to 1 R E, V B and R E determine I E and, approximately, I C. Stable bias => R E large and high gain => R E small. Gain Want gain magnitude R C /R E to be large. This implies a small R E. Gain-bias interaction Want R B to be large relative to R S, while still small relative to. (i.e. choose R B 10R S and 10 R B ) 1 R E 1 R E Want V CG = V CC I C R C to be roughly at mid-point between the V CC and the emitter bias voltage, or 1/3, 1/3, 1/3 rule. R C determines bias and gain. 3

4 Design Example Design an amplifier to meet the following specifications: Electrical specifications: v sig max =0.1V pk R S =50 Minimize cost: 1. Minimize bypass capacitors 2. Use standard 5% resistors V CC =12V 0C T 40C = A v sig max V v out max 10 Requires simulation to midband More typical gain spec: 9 A V 11 4

5 Design Step 1 (Choose R B and R E ) Choose an R B >> 10R S : R B 5000 vout 1 R E must be 10R B : 100 R E =500 Nearest standard size*: 470 R E =470 *RCA Lab: 5

6 Design Step 2 (Set R C ) vout For a gain of about -10: R C =10 R E =4.7 k Nearest standard size*: R C =4.7 k 470 =100 R B =R 1 R 2 =5 k R E =470 SPEC: v sig max =0.1V pk For a gain of -10, the collector voltage v out swings 1 V maximum, so the collector resistor bias drop could in principle be as little as 1 V. 6

7 Design Step 3 (Set bias point neglecting I B ) =100 R E = k vout 470 R B =5k R C =4.7 k Recall v sig-max = 0.1 V pk We have plenty of room - choose the collector drop conservatively to allow for bias point changes with temperature let's use: V RC V CC 3 =4.7V Thus: I C =4.7/ 4700=1mA. And (ignoring I B ): V BG =I C R E 0.7= =1.17V. 7

8 Design Step 4 (Set R 1 and R 2 ) Recall: =100 R E = k vout 470 R B =5k R C =4.7k R B =R 1 R 2 =R 1 R 2 R 1 R 2 =5 k And: V BG = R 2 R 1 R 2 V CC =1.17V Or: R 2 R 1 R 2 = V BG V CC = =

9 Design Step 4 cont. (Set R 1 and R 2 ) 4.7 k vout Substituting: R R 1 R 2 =R 2 1 =R R 1 R 1 0.1=5k 2 R 1 =50 k Standard size: R 1 =47 k =100 R E = R B =4.6 k R C =4.7k NOTE: 1 R E 47 k 10 R B =46 k R 2 Finally: = k R R 2 =0.1 47k R 2 =5222 Standard size: Revised R B : R 2 =5.1k R B =R 1 R 2 = 47k 5.1 k =4.6 k 52.1k 9

10 Design Step 5 (set C B ) - Close to the Finish! I C =1 ma =100 r =2.5k 47 k 5.1 k 4.7 k vout 470 R B in parallel with r bg => R B dominates. Estimate R in as 4.2 k. Coupling capacitor, then, should be about 420 at 20 Hz. 1 C b C B 2 f min R B 1 C B = R 2 19 F in Estimate R in : Using the RCA Lab Component 47 F r bg =r 1 R E 50 k 47 F List C B = R i n =R 2 R 1 r bg =R B r bg 4.2 k C B =23.5 F or 47 F 10

11 Final Design 23.5 uf 47 k 4.7 k vout 5.1 k

12 Multisim Simulation 20 Hz Gain Actual A V = Khz Gain 12

13 Multisim Oscilloscope Plots 13

14 Discussion 1. We neglected r e. Including the internal emitter resistance, the simulated gain becomes: A V = R C = 4700 R E r e = There is some attenuation of the signal voltage at the base. A more accurate calculation of the input attenuation: v bg R in R = 4200 R in R S 4250 v =0.988 v in =R B r bg =4.2 k sig sig Multiplying the two quantities: G= = 9.4 Close to 9.3! This fine-tuning of the estimate may be all that not helpful since we will be using 5% components to build the circuit! 14

15 Common Emitter Amplifier - Current Source Biasing 1. The current mirror sets I E (I C ). vsig 2. R b serves no purpose except to provide a path for the base current. I B = I E / v sig is the signal source. 15

16 Bias Setting Rs 1. Since R B does not interfere with the bias, the signal source can be connected to the base without need for a blocking capacitor. 2. Choose R b large compared to R S to avoid attenuating v sig. 3. Choose R ref to set I C. 16

17 Bias Setting - Continued I ref + - V BE(Qref) Choose: I C I E I ref =1mA V CC =I ref R ref V BE Qref V EE I ref = V CC V EE 0.7 R ref R ref = 23.3 =23.3k 3 10 Choose standard size: (RCA Lab Comp List) R ref =22 k 17

18 Bias Setting - Completed With the base grounded and V BE(Qamp) = 0.7 V ( I B 0 through R B ): I b 0 - Veg 5.6 k Ohm Neglect the base current through R B + V CC =V RC V CB Qamp I B R B V RC V CB This implies that there is about a 12 V drop to split across R C and V CB. Choose 6 V each. R C = V R C = 6 =6 k 3 I C 10 Choose standard size: (RCA Lab Comp List) R C =5.6 k 18

19 Gain Setting 1. Connect the source to the base. Rs 5.6 k Ohm 2. Provide a path for the small signal emitter current. 3. Choose R E for the desired gain (G = - R C /R E ). R S R B 4. C E is nearly a short circuit for f f min Calculate C E to have negligible reactance at the lowest frequency of interest f min. 19

20 Rs ib ie ESE319 Introduction to Microelectronics Gain Setting - Continued k Ohm Design for A V = 20: Choose the nearest standard size resistors for R C and R E. R E = R C 20 = Gain check: v i b = sig R S 1 r e R E v out = R C i c = R C i b v out R C 5600 v sig 1 r e R E 295 = 19 Typical 18 A V 22 20

21 R E and C E Re i e Ce overall circuit with bias ac circuit 21

22 v eg ESE319 Introduction to Microelectronics Re Design Completed The emitter circuit impedance: v eg i e = r e R E 1 j C E Choose C E to set the break i e frequency (-3dB), f min, to 20 Hz: Ce 1 =r 2 f min C e R E =295 E 1 1 C E = f min = 1 =27 F If we choose standard size (RCA Lab Comp List): C E =47 F => f min = 11.5 Hz 22

23 Multisim Bode Plots 20 Hz. Gain 1 khz. Gain 23