Exercise 1: Static JK Flip-Flop Operation

Transcription

1 Exercise 1: Static JK Flip-Flop Operation EXERCISE OBJECTIVE by measuring the output logic states for changes to the input logic states. You will verify your results with an oscilloscope. EXERCISE DISCUSSION The PR input presets (sets) the Q output to logic 1. The CLR input clears (resets) the Q output to logic 0. The data inputs are J and K. FACET by Lab-Volt 193

2 Digital Logic Fundamentals A negative clock edge is required for the outputs (Q and Q) to respond to the logic states of the J and K data inputs. a. positive clock edge is required. b. negative clock edge is required. 194 FACET by Lab-Volt

3 Q is logic 0 (L). Q is logic 1 (H). Will a logic 0 (L) at PR or CLR override the J, K, and CLK inputs? FACET by Lab-Volt 195

4 Digital Logic Fundamentals A logic 0 (L) at the PR and CLR inputs causes Q and Q to be logic 1 (H); this output condition is invalid. When PR and CLR are both logic 1 (H), the following logic states at data inputs J and K cause the following Q and Q output logic states after a negative edge of the clock signal. A logic 0 (L) at J and K results in no output change after the clock signal. 196 FACET by Lab-Volt

5 A logic 1 (H) at J and a logic 0 (L) at K result in Q equal to logic 1 (H) and Q equal to logic 0 (L) after the clock signal. A logic 0 (L) at J and a logic 1 (H) at K result in Q equal to logic 0 (L) and Q equal to logic 1 (H) after the clock signal. FACET by Lab-Volt 197

6 Digital Logic Fundamentals PR and CLR are logic 1, and J and K have complementary logic states. After the next negative edge of the clock signal, the Q output equals a. the J input logic state. b. the K input logic state. A logic 1 (H) at J and K results in the outputs changing (toggling) after every negative edge of the clock signal. 198 FACET by Lab-Volt

7 When the clock is logic 1 (H) or logic 0 (L), there is no output change. Inputs PR, CLR, J, and K are logic 1. After the next negative edge of the clock signal, the Q and Q outputs will a. change logic states. t change logic states. FACET by Lab-Volt 199

8 Digital Logic Fundamentals PROCEDURE Locate the INPUT SIGNALS, SET/RESET FLIP-FLOP, and circuit blocks. Put a two-post connector in the terminals at BLOCK SELECT. Connect A and B at the INPUT SIGNALS circuit block to A (J input) and B (K input), respectively, at the circuit block. 200 FACET by Lab-Volt

9 Connect the Q output of the SET/RESET FLIP-FLOP circuit block to the CLK input at the JK FLIP-FLOP circuit block. Set toggle switch A in the LOW position to put a logic low (0) at the J input. Set toggle switch B in the HIGH position to put a logic high at the K input. Place a two-post connector in the S (SET) position at the SET/ RESET FLIP-FLOP. This puts a logic high (1) clock signal to CLK. FACET by Lab-Volt 201

10 Digital Logic Fundamentals Connect the oscilloscope channel 1 probe to the Q output, and connect the channel 2 probe to the Q Connect the probe ground clips to a ground terminal on the circuit board. This puts a logic 0 (low) to PR. To answer the following questions, observe the logic states of Q (channel 1) and Q (channel 2) on the oscilloscope screen and as indicated by the LEDs. 202 FACET by Lab-Volt

11 Preset Output Logic States a. logic 1. b. logic 0. The Q a. logic 1. b. logic 0. Create a negative clock edge by placing the two-post connector at the SET/RESET FLIP-FLOP circuit block from S to R and back to S. Did the Q and Q outputs remain logic 1 and logic 0, respectively? Preset Output Logic States Remove the two-post connector at PRESET. Did the Q and Q outputs remain logic 1 and logic 0, respectively? Change input J to logic 1 by placing toggle switch A to HIGH, and change input K to logic 0 by placing toggle switch B to LOW. Did the Q and Q outputs remain logic 1 and logic 0, respectively? This puts a logic 0 (low) at CLEAR. FACET by Lab-Volt 203

12 Digital Logic Fundamentals Clear Output Logic States a. logic 1. b. logic 0. The Q a. logic 1. b. logic 0. Create a negative clock edge by placing the two-post connector at the SET/RESET FLIP-FLOP circuit block from S to R and back to S. Did the Q and Q outputs remain logic 0 and logic 1, respectively? Remove the two-post connector at CLEAR. Did the Q and Q outputs remain logic 0 and logic 1, respectively? The input logic states should be J at logic 1, CLK at logic 1, K at logic 0, and PR and CLR each at logic 1. The outputs should be Q at logic 0 and Q at logic 1. Be sure that the inputs 204 FACET by Lab-Volt

13 Create a negative clock edge by placing the two-post connector at the SET/RESET FLIP- FLOP circuit block from S to R and back to S. Did the outputs remain Q at logic 0 and Q at logic 1? Change input J to logic 0 by placing toggle switch A to LOW, and change input K to logic 1 by placing toggle switch B to HIGH. Did the outputs remain Q at logic 1 and Q at logic 0? Create a negative clock edge by placing the two-post connector at the SET/RESET FLIP-FLOP circuit block from S to R and back to S. Did the outputs remain Q at logic 1 and Q at logic 0? Make J and K logic 1 by placing toggle switch A to HIGH. Create a negative clock edge by placing the two-post connector at the SET/RESET FLIP-FLOP circuit block from S to R and back to S. Did the outputs change to Q at logic 1 and Q at logic 0? Create another negative clock edge by placing the two-post connector at the SET/RESET FLIP- FLOP circuit block from S to R and back to S. Did the outputs change to Q at logic 0 and Q at logic 1? a. b. FACET by Lab-Volt 205

14 Digital Logic Fundamentals CONCLUSION A logic 0 at PR is an overriding input that sets Q high. A logic 0 at CLR is an overriding input that resets Q low. If PR and CLR are logic 1 and inputs J and K have complementary logic states, the Q output changes to the logic state of J after a negative clock transition. REVIEW QUESTIONS 1. a. will change from logic 1 to logic 0 after the next clock edge. b. is logic 0. c. is logic 1. d. will change from logic 0 to logic 1 after the next negative clock edge. 2. a. will change from logic 1 to logic 0 after the next negative clock edge. b. is logic 0. c. is logic 1. d. will change from logic 0 to logic 1 after the next negative clock edge. 206 FACET by Lab-Volt

15 3. a. will be logic 0 after the next negative clock edge. b. is not affected by the logic state of the J input. c. is not the complement of Q. d. will be logic 1 after the next negative clock edge. 4. a. will be logic 0 after the next negative clock edge. b. is not affected by the logic state of the J input. c. is not the complement of Q. d. will be logic 1 after the next negative clock edge. 5. a. equal the logic state of J after the negative clock edge. b. always be logic 1. c. always be logic 0. d. change state (toggle) after every negative clock edge. FACET by Lab-Volt 207