LAB 1 BJT BIASING SCHEMES AND CHARACTERIZATION OF OPERATIONAL AMPLIFIER. Experiment 1.1 BJT biasing schemes. Experiment 1.2 Characterization of op-amp

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1 Lab 1: BJT biasing schemes and characterization of op-amp LAB 1 BJT BIASING SCHEMES AND CHARACTERIZATION OF OPERATIONAL AMPLIFIER Experiment 11 BJT biasing schemes Experiment 12 Characterization of op-amp

2 1 2 EXPERIMENT-11 BJT BIASING SCHEMES 11 OBJECTIVE 1 To sketch potential divider bias and constant current bias schemes of a transistor and understand the operation of each circuit 2 To analyze these BJT bias circuits to determine circuit voltage and current levels 3 To design these bias circuits and select appropriate standard value components 4 To trouble shoot non-operational BJT bias circuits 5 To discuss the thermal stability of BJT bias circuits and determine the effects of I CBO and V BE changes with temperature 12 HARDWA QUID a Power supply Dual variable regulated low voltage DC source b Equipments CRO, AFO, DMM (Digital Multimeter), DRBs c Resistors d Semiconductor BC107 or equivalent e Miscellaneous Bread board and wires 13 INTRODUCTION Transistors used in amplifier circuits must be biased into an on state with constant (direct) levels of collection base and emitter current and constant terminal voltages The levels of I C and V CE define the transistor dc operating point, or quiescent point The circuit that provides this state is known as a bias circuit Ideally, the current and voltage levels in bias circuits should remain absolutely constant In practical circuits these quantities are affected by the transistor current gain (h FE ) and by temperature changes The best bias circuits have the greatest stability; they hold the currents and voltages substantially constant regardless of the h FE and temperature variations

3 POTENTIAL DIVIDER BIAS Circuit Operation Vcc R1 Rc Q2 + VBE - VCE VB VE VC Fig 1-1 Potential divider bias Potential divider bias is also known as emitter current bias, or voltage divider bias A voltage divider bias circuit is shown in Fig 1-1, and the current and voltage conditions throughout the circuit are illustrated It is seen that the collector resistor (R C ) and emitter resistor (R E ) are connected in series with the transistor Thus the total dc load in series with the transistor is (Rc+R E ) and this total resistance must be used when drawing the dc load line for the circuit Resistors R 1 and R 2 constitute a voltage divider that divides the supply voltage to produce the base bias voltage (V B ) Voltage divider bias circuits are normally designed to have the voltage divider current (I 2 ) very much larger than the transistor base current (I B ) In this circumstance V B is larger unaffected by I B, so V B can be assumed to remain constant

4 1 4 Analysis Referring to fig 1-1, V B = V CC x R 2 / (R 1 + R 2 ) (11) With V B constant, the voltage across the emitter resistor is also a constant quantity, V E = V B V BE (12) This means that the emitter current is constant, I E = (V B V BE )/ R E (13) The collector current is approximately equal to the emitter current, so I C is held at a constant level I C I E (14) The collector emitter voltage is V CE = V C V E (15) and the transistor collector voltage is V C = V CC I C R C (16) V CE can also be determined as V CE V CC I C (R C + R E ) (17) Clearly with I C and I E constant, the transistor collector emitter voltage remains at a constant level It should be noted that the transistor h FE value is not involved in any of the above equations DC load line and the bias point The values of I C and V CE specify the dc operating point (Q point) and these values are written as I CQ and V CEQ respectively For the known values of the components and supply voltage, we can analytically calculate the operating point Another approach to find the Q point is the graphical method Here, we draw the straight line (the dc load line) from the above equation on the I C V CE characteristics of the transistor as shown in Fig 1-2 After calculating the base current, we identify the curve on the characteristics The intersection of the load line with this characteristic curve gives the Q-point

5 1 5 Fig 1-2 Graphical determination of Q point If the bias current changes, the Q-point will move on the load line because the characteristic curve will change Potential divider bias circuit design Bias circuit design is just a matter of determining the required voltage across each resistor and the appropriate current levels Then the resistor values are calculated by application of ohm s law Designs usually begin with specification of the supply voltage and the required levels of I C and V CE The resistor values are calculated to meet these requirements, and standard value resistors are selected When designing a voltage divider bias circuit the voltage divider current (I 2 in Fig 1-1) should be selected much larger than the transistor base current IB This makes the base voltage V B a stable quantity largely unaffected by the transistor h FE value However, a high level of I 2 result in smaller resistance values for R 1 and R 2, and this gives the circuit undesirable low input impedance A rule of thumb approach to selection of I 2 is to use a voltage divider current approximately equal to one tenth of the transistor collector current I 2 = I C / 10 (18)

6 1 6 This gives reasonably large values for R 1 and R 2 while still keeping I 2 much large than I B If V E is not specified, it should be selected much larger than the transistor V BE, V E >> V BE This is because VBE can vary from transistor to transistor, and it can also change with temperature increase or decrease Making V E very much larger than V BE minimizes the effect of V BE changes on the circuit bias conditions Typically, as another rule of thumb, V E is selected as 5v regardless of the supply voltage When V CC is low, V E can be as low as 3 V The equations used for calculating each resistor value are: R 1 = (V CC V B ) / I 2 R 2 = V B / I 2 R C = (V CC V CE V E )/ I C R E V E / I C Design problem Design the voltage divider bias circuit to have V CE = V E = 5v and I C = 5mA when the supply voltage is 15v Assume the transistor h FE is 100 Design procedure Vcc=+15V R1 18K 57V Rc 1K 10V Q V VBE - - 5V 12K 1K R R VE VE 5V = = = KΩ (standard value) I I 5mA E 1 E C Fig 1-3 Voltage divider bias circuit designed ( VCC VCE VE ) 15V 5V 5V = = = KΩ (standard value) I 5mA C 1 C

7 1 7 From eq (18), I I C = 10 2 = 500µ A From eq (12), V B = V E +V BE = 5V+07V = 57V R 2 VB 57V = = = 114KΩ (use 12KΩ standard value) I 500µ A 2 R 1 ( VCC VB ) 15V 57V = = = 186KΩ I 500µ A 2 (use 18kΩ standard value) 15 TROUBLE SHOOTING BJT BIAS CIRCUITS When a bias circuit is constructed in a laboratory situation, the supply voltage (V CC ) and the voltage levels at the transistor terminals (V C V B and V E ) should be measured with respect to the ground or negative supply terminal when the measured voltages are not as expected, the circuit must be further investigated to locate the fault The following is a list of errors that commonly occur Power supply not switched on Power supply current limiter control incorrectly set Cables incorrectly connected to the power supply VOM (volt ohm milliammeter) function incorrectly selected Wrong VOM terminals used Incorrect component connections Resistor in wrong places Figure (14) shows unsuitable measured voltages and probable errors in a voltage divider bias circuit

8 Vcc 1 8 R1 open circuited R1 Rc Rc short circuited Transistors terminals open circuited short circuited + Q2 VBE - Vc=Vcc open circuited (a) Collector voltage equal to supply voltage Vcc R1 Rc Transistor terminals short circuited R1 & interchanged open circuited + VBE - Q2 VE Vc=VE (b) Collector voltage equal to emitter voltage Fig 1-4 Unsatisfactory measured voltages on a voltage divider bias circuit, and probable circuit faults

9 THERMAL STABILITY OF BIAS CIRCUITS Thermal stability is the measure of how stable I C and V CE remain when the circuit temperature changes, sine many transistor circuits are required to operate over a wide temperature range The base-emitter voltage (V BE ) and the collectorbase reverse saturation current (I CBO ) are the two temperature sensitive quantities that largely determine the thermal stability of a transistor circuit The EB and CB junction have the temperature characteristics as stated below: For a Si transistor, V BE changes by approximately -18 mv/ o C I CBO approximately doubles for every 10 o C rise in temperature changes in I CBO and VBE produce Significant changes in I C Circuit Q point Possibility of thermal runaway Stability factor The stability factor (S) of a circuit is the ration of the change in collector current to the change in collector base leakage current S = I C / I CBO or, I C = S x I CBO (19) The value of S depends on the circuit configuration and on the resistor values A stability factor of 50 (or larger) is considered poor, while a factor of 10 or less is considered good For voltage divider bias, the stability factor can be shown to be hfe S = 1 + (110) hfe 1 + R + R R E 1 The change in I CBO over a given temperature range can be calculated by recalling that I CBO doubles for every 10 o C increase in temperature The temperature change ( T) is divided by 10 to give the number of 10 o C changes (n) If the starting level of collector-base leakage current is I CBO (I), the new level is I CBO (2) = I CBO (1) x 2 n (111) 2

10 1 10 The I CBO change and the circuit stability factor can be used to determine the change in I C Then the resulting V CE change can be investigated Effect of V BE change Consider the voltage divider bias circuit designed in Fig13 From eq (13), I C I E = (V B V BE ) / R E Assuming that V B remains substantially constant, an equation for I C change with V BE change can be writer as I C I E = V BE / R E (112) when the change in I C is determined, then the result mg V CE change can be investigated Example 1-1 Calculate the stability factors for the voltage divider bias circuit designed in Fig 13 Also determine the IC change produced when the circuit temperature increase from 25 o C to 125 o C by the effect of (i) I CBO, which is equal to 15nA at 25 o C (ii) V BE changes Solution Calculation of stability factor hfe S = 1 + = hfe 1 + R + R R E S = 1+ = K 1+ 1K + 18K 12K Effect of I CBO Changes T = 125 o C 25 o C = 100 o C or, the number of 10 o C changes, in = 100 o C / 10 o C =10 From eq (111), I CBO (2) = I CBO (1) x 2 n = 15nA x 210 = 1536µA I CBO = I CBO (2) I CBO (1) = 1536µA - 15µA = 15345µA from eq(19) I C = S x I CBO = 765 x 15345µA = 11739µA

11 1 11 Effect of V BE changes V BE = T x (1-8mV/ o C) = 100 o C x 18mV/ o C = 180mV From eq (1-12), I C = V BE /R E = 180mV / 1K = 180µA Diode compensation The use of a diode to compensate for VBE changes is illustrated in Fig 1-5 Vcc R1 Rc + + VBE VD1 - D1 - Q1 Fig 1-5 A diode can be used to compensate for VBE changes in a voltage divider bias circuit In this case, V B = V + V D1 (113) and, I C I E = (V + V D1 V BE ) / R E (114) When VBE changes by VBE, the diode voltage changes by an approximately equal amount ( V D1 ) V BE and V D1 tend to cancel each other, leaving I C largely constant at I C I E = V / R E (115)

12 CONSTANT CURNT BIASING The fabrication of resistors and capacitors in integrated circuits is not economical Thus, circuits are fabricated using the maximum number of transistors and the minimum number of resistors and capacitors The biasing arrangements used in the integrated circuits use a constant current source (also called current mirror) to maintain Q-point stable Fig 1-6(a) shows a simple realization of the current source and Fig 1-6(b) shows a simple realization of the current source, I +VCC RC Q1 1k IL -VEE Fig 1-6 (a) Constant current biasing (b) Simple realization of current source (current mirror) The current mirror is a dc network in which the current through the boad is the mirror image of another current of the same network If the reference current of the network is changed, the current through the load will also change A basic current mirror constructed using two back-to back npn transistors is shown in Fig 1-6(b) the load current is the collector current of Q2, and the reference collector current of Q3 Note, in particular, that the collector of Q1 is connected directly to the base of the same transistor, establishing the same potential at each point The result is that V C3 = V BE3 = V BE2 = 07V The controlling element is resistor R If you change its value, you can change the reference current

13 1 13 Once the resistance is set, the collector current of Q2 will immediately change to the new level The operation of the mirror network is totally dependent on the fact that Q2 and Q3 are matched transistors, ie, transistors with very similar characteristics Therefore, I F ( VCC VEE VBE ) = I L = (116) R We can connect this simulated current source in place of I L in Fig 1-6(a) and get a stable Q- point Note that the current I L is independent of h FE and R B This gives us liberty in choosing the value of R B 18 P-LAB QUESTIONS 1) What is faithful amplification? What are the conditions to be fulfilled to achieve faithful amplification in a transistor amplifier? 2) What do you understand by transistor biasing? What is its need? 3) What do you understand by stabilization of Q-point? 4) Define Q-point and explain the concept of dc load line 5) Analyze the voltage divider bias circuit in Fig 1-7 to determine the transistor terminal voltages and currents (ie, V B, V C, V E, V BC, V CE, I C and I E ) Draw the load line and plot the Q-point Also determine whether the transistor is biased in cut-off, saturation, or the linear region +VCC=18V R1 Rc 33K 12K Q1 12K 1K Fig 1-7 Voltage divider bias for problem 1-5 6) Design a voltage divider bias circuit using a BC107 transistor to have V CE = 4V, V E = 5V and I C = 13mA, the supply is V CC = 18V (Note: Refer data sheet for hie and hfe values)

14 1 14 7) Calculate the stability factor for the voltage divider bias circuit designed in problem 1-6 8) Determine the Q-point change (ie, I C change & V CE change) produced in VD bias circuit designed in problem 1-6 when the circuit temperature in creased from 50 o C to 150 o C, and I CBO = 10nA at 50 o C 9) Determine the Q-point change produced in voltage divider bias circuit designed in problem 1-6 by the effect of VBE changes over a temperature range of 50 o C to 150 o C 10) Calculate the mirrored current I in the circuit of Fig1-8 Fig 1-8 Current mirror circuit for problem EXPERIMENT (1) Voltage divider 11 Determine the values of R 1, R 2, R C and R E from the design problem 6 in the prelab question 12 Assemble the circuit use BC107 transistor or equivalent If the exact values of the components are not available, pickup the near by standard values Measure hie and h FE of the transistor used If the parameters of the transistor do not match the design specifications, recalculate the component values with these parameters 13 Measure the Q-point For measuring the Q-point, follow the procedure given below: Measure the voltage V C between the collector and the common terminal and then the voltage V E between emitter and common terminal The difference (V C V E ) gives V CE The collector current I C is given by (V CC -V C ) / R C compare the measured values with the designed values 14 Follow the same procedure the measure other transistor terminal currents and voltage

15 1 15 (2) Constant current biasing 21 From eq (1-16) determine the value of R for the constant current biasing circuit as shown in Fig 1-8 using the following data R C = 2KΩ, R B = 220KΩ, V CC = 15V, V EE = 15V, V BE = 07V, I C = 5mA Assume large h FE Neglect I CBO 22 Assemble the circuit use the BC107 transistors If the exact values of the components are not available, pick up the nearby standard values Measure hie and h FE of the transistor used If the transistors do not match the design specifications, recalculate the component values with these parameters Fig 1-8 Constant current biasing circuit 23 Measure the value of I CQ and V CEQ as per procedure given in step 13 Compare the measured value with the design parameter Tabulate the readings 110 POSTLAB QUESTIONS 1 In the implementation of voltage divider bias circuit change the value of R 1 to R 1 / 2 and then to 2R 1 and measure the Q-point in each case Comment on the changes in the Q- point values 2 In the implementation of constant current biasing circuit, increase the value of R by 1KΩ and measure the I C of Q 1 Now, decrease the value of R by 1KΩ and measure the I C of Q 1 Comment on the change in I C in each case

16 The measurements appearing in Fig 1-9 reveal that the network is not operating properly Be specific in describing why the levels obtained reflect a problem with the expected network behavior In other words, the level obtained reflect a very specific problem in each case +VCC=16V +VCC=16V R1 91K Rc 36K R1 91K Rc 36K 94V Beta= V Beta=100 4V 18K 12K 18K 12K (a) Fig 1-9 (b) 4 For the VDB circuit implemented in the experiment, answer the following questions a Does V C increase or decrease if R 1 is increased? b Does I C increase or decrease if β(h FE ) is reduced? c Does I C increase or decrease if V CC is reduced? d What happens to V CE if the transistor is replaced one with larger β (h FE )? e What happens to I C (sat) if β is increased? f What happens to V CE if the ground leg of R 2 opens? g What happens to V CE if the transistor EB junction fails by becoming open? h What happens to V CE if the transistor EB junction fails by becoming a short i How will V E be affected when replacing the collector resistor with one whose resistance is at the lower end of the tolerance range? j If the transistor collector junction becomes open, what will happen to V E? k What might cause V CE to become nearly 18V? l Analyze the circuit to investigate the effect of interchanging the voltage divider resistors