Benefits of SRAM design with Tunnel FETs
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1 Benefits of SRAM design with Tunnel FETs Costin Anghel, Andrei Vladimirescu, Amara Amara Institut Superieur d'electronique de Paris (Paris, FR), 1/41
2 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 2/41
3 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 3/41
4 TFET vs. CMOS CMOS n- type TFET n- type Source Gate Oxide Drain Source Gate Oxide Drain n + i n + p + i n + CMOS: Pros.: classical device I ON within the ITRS targets Cons.: power issue TFET: Pros.: Extremely Low I OFF SS below 60mV/dec Cons.: Low I ON R&D needed 4/41
5 TFET vs. CMOS TFET: ideal device Low I OFF Steep characteristic è improved I ON /I OFF ratio I ON is NOT so important as long as: I EFF is carefully optimized A.M. Ionescu, H. Riel, Nature, Vol. 479, pp , /41
6 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 6/41
7 Homo vs. Hetero Junction TFET Homo- Junc5on TFET Source Gate p + i n + Oxide Drain Source Hetero- Junc5on TFET Gate p + i n + Oxide Drain Pros.: Easier to fabricate Low density of traps Some demonstrators already present Cons.: Lower I ON current Critical research mass not attained Pros.: Theoretically higher I ON Theoretically lower V DD Critical research mass attained Cons.: High density of traps Majority of demonstrators show deceiving performance 7/41
8 Forward Output Characteris5cs Homo- Junc5on TFET Hetero- Junc5on TFET Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED /41
9 Reverse Output Characteris5cs UNIDIRECTIONAL behaviour Homo- Junc5on TFET Hetero- Junc5on TFET Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED /41
10 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 10/41
11 TFET circuits the Ring oscillator TFET CMOS PTM TFET presents over and under-shoots due to its high Miller capacitance. 11/41
12 TFET circuits the Ring oscillator Frequency (GHz) PTM TFET - low V OFF TFET Supply Voltage (V) The TFET circuits are not as fast as CMOS, however they dissipate significant less static power Adam Makosiej et al. ISCAS, /41
13 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 13/41
14 SRAM what is this memory good for? Why do we really need SRAMs? - SPEED Which are the other requirements for SRAM? - Low power (static and dynamic) - Compact cell (low area) 14/41
15 TFET circuits matrix The power consump<on has to be reduced for all cells during all opera5on modes (i.e. read, write and reten)on) ACC accessed; HS half selected; WD write disturb; RET reten<on 15/41
16 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 16/41
17 Half selec5on in CMOS ACC cell HS cell 0 1 VDD VDD VDD VDD activation leads to leakage in the HS cells 17/41
18 TFET- based SRAM cells CMOS 6T cell TFET 6T cell The easiest way to build a TFET SRAM cell mimic 6T CMOS cell 18/41
19 TFET benefit è reduced leakage in HS cells ACC cell HS cell 0 1 VSS VSS VSS + ΔV VSS + ΔV TFET unidirec<onality HELPS reducing parasi<c current in HS cells 19/41
20 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 20/41
21 TFET- based SRAM cells CMOS 6T cell TFET 6T cell Saripalli et al. Proc. of Nanoarch 2011 TFET unidirec<onal how to connect the access transistors? 21/41
22 TFET circuits 6T SRAM Inward access TFETs READ WRITE Doesn t work in write position of the source of the access transistors Outward access TFETs Could work but problems see next slides Kim et al., ISLPED /09/ /11/2013 NanoInnov ESSDERC 22/41
23 Why 6T outward cell doesn t work 0.1 Homo- Junc5on TFET Hetero- Junc5on TFET SNM Values [V] 0.05 WSNM RSNM Pull Up Ratio (PU) Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED 2009 Extremely low SNMs regardless the TFET technology!!! need different topology for TFET SRAM cell 23/41
24 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 24/41
25 SRAM with separated read port CMOS 8 T cell TFET 7T cell Verma, Chandrakasan, IEEE J. Solid- State Circuits, 43, , Kim et al. Proc. of ISLPED 2009 Ø Use the unidirectional condution of TFET to reduce the no. of transistors 25/41
26 Why 7T TFET cell doesn t work Reten5on Write BLL=0V BLL=0V BLL=0V BLL=VDD Kim et al. Proc. of ISLPED 2009 Ø In write one access transistor is reversed biased è its current is NOT controlled by its gate. 26/41
27 Why 7T TFET cell doesn t work Homo- Junc5on TFET Hetero- Junc5on TFET Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED /41
28 Why 7T TFET cell doesn t work Outward access TFETs leakage problem Kim et al., ISLPED 2009 (D. Blaauw Univ. Of Michigan). 28/41
29 Why 7T TFET cell doesn t work Outward access TFETs leakage problem BLL (GND) VDD BLR (VDD) BLL (GND) VDD BLR (VDD) BLL (GND) VDD BLR (VDD) Leakage TR1 LD1 LD2 1 0" DR1 DR2 TR2 I leak TR1 LD1 LD2 1 0" DR1 DR2 TR2 I leak TR1 LD1 LD2 1 0" DR1 DR2 TR2 I leak GND GND GND VDD VDD VDD WRITE Word LD1 TR1 1 I write DR1 "0" LD2 DR2 TR2 I leak LD1 TR1 1 I write DR1 "0" LD2 DR2 TR2 I leak LD1 TR1 1 I write DR1 "0" LD2 DR2 TR2 I leak GND VDD GND VDD GND VDD Leakage TR1 LD1 DR1 1 0" LD2 DR2 TR2 I leak TR1 LD1 DR1 1 0" LD2 DR2 TR2 I leak TR1 LD1 DR1 1 0" LD2 DR2 TR2 I leak GND GND GND Leakage - cumulative and depends on the size of the written word 29/41
30 Why 7T TFET cell doesn t work Outward access TFETs leakage problem How important is this leakage at the cell level? Our sims: 32 na in a cell in write disturb EX: 1k bit 992 x 32nA leakage in the worst case 30µA 30/41
31 Why 7T TFET cell doesn t work Outward access TFETs capacitance discharge problem 0 BLL (GND) TR1 LD1 VDD 0 1 0" LD2 DR1 DR2 BLR (VDD) 0 TR2 I leak 1 0 TR2 1 GND VDD LD1 LD2 High capacitance mode Charging TR2 0 TR1 1 I write DR1 GND VDD "0" DR2 TR2 I leak LD1 LD2 TR1 1 0" TR2 DR1 DR2 I leak GND 31/41
32 Why 7T TFET cell doesn t work Outward access TFETs capacitance discharge problem How important is this leakage at the cell level? Our sims: 300 na in a cell in write disturb è Flipping BLL and BLR is not a good option in TFET cells 32/41
33 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 33/41
34 Other TFET cells Different TFET SRAM cells were proposed by several groups They are all based on flipping the bitlines during write operation Singh et al., 15th Asia and South Pacific Design Automation Conference (ASP-DAC), /41
35 Other TFET cells Different TFET SRAM cells were proposed by several groups They are all based on flipping the bitlines during write operation Saripalli et al., Nanoarch 2011 (S. Datta, Penn State & Intel). 35/41
36 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 36/41
37 TFET circuits new design Idea: Do not flip the bitlines during WRITE but use two wordlines BLL (VDD) VDD BLR (0.6V/GND) WRITE 1 1 LD1 LD2 1 WRITE 0 TR1 TR2 2 DR1 V1 V2 DR2 TR3 TR4 2 GND Adam Makosiej et al. ISCAS, No Half Selection or Write Disturb issues 37/41
38 Our 8T design performance VDD=1V VDD=1V Adam Makosiej et al. ISCAS, estimated operation speed: 300MHz for read and 1GHz for write - 5 orders of magnitude lower average leakage with respect to low power PTM 38/41
39 Comparison with CMOS Fukuda et al, ISSCC, 2014 (Toshiba) CMOS TFET Technology (nm) Leakage (fa/cell) Speed 7ns 3.3ns (read) 1ns (write) VDD (V) Cell Size (µm 2 ) Scalable No Yes - TFET cell offers comparable performance for the cell - TFET cell size is 6.38 times smaller with respect to CMOS cell 39/41
40 Conclusion: - Half Selection and Write Disturb avoided - Reasonable margins obtained - Reasonable speed obtained - Very low static power obtained - Reduced area - obtained TFET can replace the CMOS in SRAM for low power applications 40/41
41 Many Thanks to: - Hraziia, Adam Makosiej, Navneet Gupta - Prof. Andrei Vladimirescu, Prof. Amara Amara - Cyrille Le Royer CEA LETI - Olivier Thomas CEA LETI Thank you for your attention! 41/41
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