Benefits of SRAM design with Tunnel FETs

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Benefits of SRAM design with Tunnel FETs"

Transcription

1 Benefits of SRAM design with Tunnel FETs Costin Anghel, Andrei Vladimirescu, Amara Amara Institut Superieur d'electronique de Paris (Paris, FR), 1/41

2 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 2/41

3 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 3/41

4 TFET vs. CMOS CMOS n- type TFET n- type Source Gate Oxide Drain Source Gate Oxide Drain n + i n + p + i n + CMOS: Pros.: classical device I ON within the ITRS targets Cons.: power issue TFET: Pros.: Extremely Low I OFF SS below 60mV/dec Cons.: Low I ON R&D needed 4/41

5 TFET vs. CMOS TFET: ideal device Low I OFF Steep characteristic è improved I ON /I OFF ratio I ON is NOT so important as long as: I EFF is carefully optimized A.M. Ionescu, H. Riel, Nature, Vol. 479, pp , /41

6 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 6/41

7 Homo vs. Hetero Junction TFET Homo- Junc5on TFET Source Gate p + i n + Oxide Drain Source Hetero- Junc5on TFET Gate p + i n + Oxide Drain Pros.: Easier to fabricate Low density of traps Some demonstrators already present Cons.: Lower I ON current Critical research mass not attained Pros.: Theoretically higher I ON Theoretically lower V DD Critical research mass attained Cons.: High density of traps Majority of demonstrators show deceiving performance 7/41

8 Forward Output Characteris5cs Homo- Junc5on TFET Hetero- Junc5on TFET Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED /41

9 Reverse Output Characteris5cs UNIDIRECTIONAL behaviour Homo- Junc5on TFET Hetero- Junc5on TFET Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED /41

10 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 10/41

11 TFET circuits the Ring oscillator TFET CMOS PTM TFET presents over and under-shoots due to its high Miller capacitance. 11/41

12 TFET circuits the Ring oscillator Frequency (GHz) PTM TFET - low V OFF TFET Supply Voltage (V) The TFET circuits are not as fast as CMOS, however they dissipate significant less static power Adam Makosiej et al. ISCAS, /41

13 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 13/41

14 SRAM what is this memory good for? Why do we really need SRAMs? - SPEED Which are the other requirements for SRAM? - Low power (static and dynamic) - Compact cell (low area) 14/41

15 TFET circuits matrix The power consump<on has to be reduced for all cells during all opera5on modes (i.e. read, write and reten)on) ACC accessed; HS half selected; WD write disturb; RET reten<on 15/41

16 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 16/41

17 Half selec5on in CMOS ACC cell HS cell 0 1 VDD VDD VDD VDD activation leads to leakage in the HS cells 17/41

18 TFET- based SRAM cells CMOS 6T cell TFET 6T cell The easiest way to build a TFET SRAM cell mimic 6T CMOS cell 18/41

19 TFET benefit è reduced leakage in HS cells ACC cell HS cell 0 1 VSS VSS VSS + ΔV VSS + ΔV TFET unidirec<onality HELPS reducing parasi<c current in HS cells 19/41

20 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 20/41

21 TFET- based SRAM cells CMOS 6T cell TFET 6T cell Saripalli et al. Proc. of Nanoarch 2011 TFET unidirec<onal how to connect the access transistors? 21/41

22 TFET circuits 6T SRAM Inward access TFETs READ WRITE Doesn t work in write position of the source of the access transistors Outward access TFETs Could work but problems see next slides Kim et al., ISLPED /09/ /11/2013 NanoInnov ESSDERC 22/41

23 Why 6T outward cell doesn t work 0.1 Homo- Junc5on TFET Hetero- Junc5on TFET SNM Values [V] 0.05 WSNM RSNM Pull Up Ratio (PU) Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED 2009 Extremely low SNMs regardless the TFET technology!!! need different topology for TFET SRAM cell 23/41

24 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 24/41

25 SRAM with separated read port CMOS 8 T cell TFET 7T cell Verma, Chandrakasan, IEEE J. Solid- State Circuits, 43, , Kim et al. Proc. of ISLPED 2009 Ø Use the unidirectional condution of TFET to reduce the no. of transistors 25/41

26 Why 7T TFET cell doesn t work Reten5on Write BLL=0V BLL=0V BLL=0V BLL=VDD Kim et al. Proc. of ISLPED 2009 Ø In write one access transistor is reversed biased è its current is NOT controlled by its gate. 26/41

27 Why 7T TFET cell doesn t work Homo- Junc5on TFET Hetero- Junc5on TFET Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED /41

28 Why 7T TFET cell doesn t work Outward access TFETs leakage problem Kim et al., ISLPED 2009 (D. Blaauw Univ. Of Michigan). 28/41

29 Why 7T TFET cell doesn t work Outward access TFETs leakage problem BLL (GND) VDD BLR (VDD) BLL (GND) VDD BLR (VDD) BLL (GND) VDD BLR (VDD) Leakage TR1 LD1 LD2 1 0" DR1 DR2 TR2 I leak TR1 LD1 LD2 1 0" DR1 DR2 TR2 I leak TR1 LD1 LD2 1 0" DR1 DR2 TR2 I leak GND GND GND VDD VDD VDD WRITE Word LD1 TR1 1 I write DR1 "0" LD2 DR2 TR2 I leak LD1 TR1 1 I write DR1 "0" LD2 DR2 TR2 I leak LD1 TR1 1 I write DR1 "0" LD2 DR2 TR2 I leak GND VDD GND VDD GND VDD Leakage TR1 LD1 DR1 1 0" LD2 DR2 TR2 I leak TR1 LD1 DR1 1 0" LD2 DR2 TR2 I leak TR1 LD1 DR1 1 0" LD2 DR2 TR2 I leak GND GND GND Leakage - cumulative and depends on the size of the written word 29/41

30 Why 7T TFET cell doesn t work Outward access TFETs leakage problem How important is this leakage at the cell level? Our sims: 32 na in a cell in write disturb EX: 1k bit 992 x 32nA leakage in the worst case 30µA 30/41

31 Why 7T TFET cell doesn t work Outward access TFETs capacitance discharge problem 0 BLL (GND) TR1 LD1 VDD 0 1 0" LD2 DR1 DR2 BLR (VDD) 0 TR2 I leak 1 0 TR2 1 GND VDD LD1 LD2 High capacitance mode Charging TR2 0 TR1 1 I write DR1 GND VDD "0" DR2 TR2 I leak LD1 LD2 TR1 1 0" TR2 DR1 DR2 I leak GND 31/41

32 Why 7T TFET cell doesn t work Outward access TFETs capacitance discharge problem How important is this leakage at the cell level? Our sims: 300 na in a cell in write disturb è Flipping BLL and BLR is not a good option in TFET cells 32/41

33 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 33/41

34 Other TFET cells Different TFET SRAM cells were proposed by several groups They are all based on flipping the bitlines during write operation Singh et al., 15th Asia and South Pacific Design Automation Conference (ASP-DAC), /41

35 Other TFET cells Different TFET SRAM cells were proposed by several groups They are all based on flipping the bitlines during write operation Saripalli et al., Nanoarch 2011 (S. Datta, Penn State & Intel). 35/41

36 Outline: A closer look on the TFET characteristics TFET vs. CMOS TFET vs. TFET What should we expect as benefit from TFET? First benchmark ring oscillator Second benchmark SRAM cells - Half Selection issue Conclusion - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines 36/41

37 TFET circuits new design Idea: Do not flip the bitlines during WRITE but use two wordlines BLL (VDD) VDD BLR (0.6V/GND) WRITE 1 1 LD1 LD2 1 WRITE 0 TR1 TR2 2 DR1 V1 V2 DR2 TR3 TR4 2 GND Adam Makosiej et al. ISCAS, No Half Selection or Write Disturb issues 37/41

38 Our 8T design performance VDD=1V VDD=1V Adam Makosiej et al. ISCAS, estimated operation speed: 300MHz for read and 1GHz for write - 5 orders of magnitude lower average leakage with respect to low power PTM 38/41

39 Comparison with CMOS Fukuda et al, ISSCC, 2014 (Toshiba) CMOS TFET Technology (nm) Leakage (fa/cell) Speed 7ns 3.3ns (read) 1ns (write) VDD (V) Cell Size (µm 2 ) Scalable No Yes - TFET cell offers comparable performance for the cell - TFET cell size is 6.38 times smaller with respect to CMOS cell 39/41

40 Conclusion: - Half Selection and Write Disturb avoided - Reasonable margins obtained - Reasonable speed obtained - Very low static power obtained - Reduced area - obtained TFET can replace the CMOS in SRAM for low power applications 40/41

41 Many Thanks to: - Hraziia, Adam Makosiej, Navneet Gupta - Prof. Andrei Vladimirescu, Prof. Amara Amara - Cyrille Le Royer CEA LETI - Olivier Thomas CEA LETI Thank you for your attention! 41/41

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department

More information

A Low Power SRAM Base on Novel Word-Line Decoding

A Low Power SRAM Base on Novel Word-Line Decoding International Journal of Computer, Electrical, Automation, Control and Information Engineering Vol:, No:3, 008 A Low Power SRAM Base on Novel Word-Line Decoding Arash Azizi Mazreah, Mohammad T. Manzuri

More information

Novel Approaches to Low Leakage and Area Efficient VLSI Design. Professor Md. Shafiqul Islam, PhD

Novel Approaches to Low Leakage and Area Efficient VLSI Design. Professor Md. Shafiqul Islam, PhD Novel Approaches to Low Leakage and Area Efficient VLSI Design A Thesis Submitted to the Department of Electrical and Electronic Engineering in Partial Fulfillment of the Requirements for the Degree of

More information

Outline. Power and Energy Dynamic Power Static Power. 4th Ed.

Outline. Power and Energy Dynamic Power Static Power. 4th Ed. Lecture 7: Power Outline Power and Energy Dynamic Power Static Power 2 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average

More information

SRAM design challenges in nano-scale CMOS

SRAM design challenges in nano-scale CMOS SRAM design challenges in nano-scale CMOS Vivek De Circuits Research Lab Acknowledgment: M. Agostinelli, A. Farhang, F. Hamzaoglu, A. Keshavarzi, D. Khalil, M. Khellah, N-S. Kim, G. Pandya, S. Rusu, D.

More information

Bit Line Bias. Sense Amps. Column Decode BR 9/01. Memory Array

Bit Line Bias. Sense Amps. Column Decode BR 9/01. Memory Array it Line ias Row Address Row Decode Cell Memory Organization Word lines (1 per row) Column Address Sense Amps Column Decode it lines (2 per column) Data lines Memory Array Typically want an aspect ratio

More information

CMOS Thyristor Based Low Frequency Ring Oscillator

CMOS Thyristor Based Low Frequency Ring Oscillator CMOS Thyristor Based Low Frequency Ring Oscillator Submitted by: PIYUSH KESHRI BIPLAB DEKA 4 th year Undergraduate Student 4 th year Undergraduate Student Electrical Engineering Dept. Electrical Engineering

More information

13. Memories. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016

13. Memories. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 13. Memories Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 October 12, 2016 ECE Department, University of Texas at Austin Lecture

More information

Performance Analysis of different MUX for FPGA

Performance Analysis of different MUX for FPGA . Performance Analysis of different MUX for FPGA P rof. S. M. Turkane, N.V.Ambedkar, S.V.K aname, T.V.K harde 1 Prof, Ele c tr o n ic s a n d Te le c o mmu n ic a tio n, PREC Loni, M a h a r a s h tr a,

More information

Dynamic Combinational Circuits

Dynamic Combinational Circuits Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) James Morizio 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

More information

DESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE

DESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE DESIGN OF LOW POWER SRAM USING NEGATIVE BIAS TEMPERATURE INSTABILITY TECHNIQUE 1 SWATHI TANGELLA, 2 PREMA KUMAR MEDAPATI 1 M.Tech Student, Department of ECE, Shri Vishnu Engineering College for Women 2

More information

ECE 651: SRAM 1. Outline. Memory Arrays SRAM Architecture. SRAM Cell Decoders Column Circuitry Multiple Ports. Serial Access Memories

ECE 651: SRAM 1. Outline. Memory Arrays SRAM Architecture. SRAM Cell Decoders Column Circuitry Multiple Ports. Serial Access Memories ECE 651: SRAM 1 Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories ECE 651: SRAM 2 Memory Arrays Memory Arrays Random Access Memory Serial

More information

Low Power and Low Frequency CMOS Ring Oscillator Design

Low Power and Low Frequency CMOS Ring Oscillator Design Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2015, 2(7): 82-87 Research Article ISSN: 2394-658X Low Power and Low Frequency CMOS Ring Oscillator Design Venigalla

More information

Keywords: SAEN (sense enable signal), BB (bit- bar), BL (bit- line), SOC (system on chip)

Keywords: SAEN (sense enable signal), BB (bit- bar), BL (bit- line), SOC (system on chip) Volume 4, Issue 5, May 2014 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Analytical Study

More information

Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM)

Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM) Module 6 : Semiconductor Memories Lecture 28 : Static Random Access Memory (SRAM) Objectives In this lecture you will learn the following SRAM Basics CMOS SRAM Cell CMOS SRAM Cell Design READ Operation

More information

Semiconductor Memories

Semiconductor Memories Chapter 8 Semiconductor Memories (based on Kang, Leblebici. CMOS Digital Integrated Circuits 8.1 General concepts Data storage capacity available on a single integrated circuit grows exponentially being

More information

Memory Technology: Putting the nano in your ipod

Memory Technology: Putting the nano in your ipod Memory Technology: Putting the nano in your ipod Eric Pop Dept. of Electrical & Computer Engineering http://poplab.ece.uiuc.edu 1 Applications of Memory 1 Gigabyte = 1 GB = 1 billion bytes 1024 3 bytes

More information

Outline. Lecture 19: SRAM. Memory Arrays. Array Architecture

Outline. Lecture 19: SRAM. Memory Arrays. Array Architecture Outline Lecture 19: SRAM Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories 2 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory

More information

New Single-Phase Adiabatic Logic Family

New Single-Phase Adiabatic Logic Family New Single-Phase Adiabatic Logic Family Mihail Cutitaru, Lee A. Belfore, II Department of Electrical and Computer Engineering, Old Dominion University, Norfolk, VA, 23529 USA Abstract Power dissipation

More information

A Study of Different Types of Voltage & Current Sense Amplifiers used in SRAM

A Study of Different Types of Voltage & Current Sense Amplifiers used in SRAM A Study of Different Types of Voltage & Current Sense Amplifiers used in SRAM Meenu Rani Garg 1, Anu Tonk 2 M.Tech VLSI Design, Department of Electronics, YMCAUST, Faridabad, India 1,2 Abstract: The paper

More information

An Efficient Implementation of Multiplexer Based Flip-Flop in Subthreshold Region

An Efficient Implementation of Multiplexer Based Flip-Flop in Subthreshold Region An Efficient Implementation of Multiplexer Based Flip-Flop in Subthreshold Region Bhanu Prasad Nimmagadda 1, M. Murali Krishna 2, Ch. Sumanth Kumar 3 and G.V.K.Sharma 4 1 Department of ECE, GITAM Institute

More information

SRAM Architecture. Vishal Saxena, Boise State University Department of Electrical and Computer Engineering

SRAM Architecture. Vishal Saxena, Boise State University Department of Electrical and Computer Engineering Department of Electrical and Computer Engineering SRAM Architecture Vishal Saxena, Boise State University (vishalsaxena@boisestate.edu) Vishal Saxena -1- Outline Memory Arrays SRAM Architecture SRAM Cell

More information

EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell

EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell EE 4432 VLSI Design Layout and Simulation of a 6T SRAM Cell Mat Binggeli October 24 th, 2014 Overview Binggeli Page 2 The objective of this report is to describe the design and implementation of a 6-transistor

More information

DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY B.CHINNARAO 1, B.FRANCIS 2 & Y.APPARAO 3 1 Dept, Electronics & Communication Engg., Gokul Institute of Technology & Sci. 2 E.C.E Dept.,

More information

Energy-Efficient Manycore Architectures for Big Data

Energy-Efficient Manycore Architectures for Big Data Energy-Efficient Manycore Architectures for Big Data Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu BPOE April 2015 Wanted: Energy-Efficient Computing

More information

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, Junh Ho Ahn, Richard Strong, Jay B. Brockman, Dean M Tullsen, Norman Jouppi MICRO 2009

More information

Design and Performance Comparison of Average 8T SRAM with Existing 8T SRAM Cells

Design and Performance Comparison of Average 8T SRAM with Existing 8T SRAM Cells Design and Performance Comparison of Average 8T with Existing 8T Cells 1 Bini Joy, 2 Sathia Priya.M, 3 Akshaya.N 4 Ruth Anita Shirley.D 1,2,3,4 PG Students/DEPT OF ECE, SNS College of Technology, Coimbatore,

More information

RS FLIP FLOP BASIC OPERATION. INEL 4207 Digital Electronics - M. Toledo

RS FLIP FLOP BASIC OPERATION. INEL 4207 Digital Electronics - M. Toledo RS FLIP FLOP BASIC OPERATION INEL 427 Digital Electronics - M. Toledo Figure 6. A 2 M+N -bit memory chip organized as an array of 2 M rows 2 N columns. Figure 6. (a) Basic latch. (b) The latch with the

More information

RS FLIP FLOP BASIC OPERATION

RS FLIP FLOP BASIC OPERATION RS FLIP FLOP BASIC OPERATION INEL 427 Digital Electronics - M. Toledo Wednesday, October 7, 2 Wednesday, October 7, 2 Figure 6. A 2 M+N -bit memory chip organized as an array of 2 M rows 2 N columns. Wednesday,

More information

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications Gianluca Traversi a,c, F. De Canio b,c, L. Gaioni a, M. Manghisoni a,c, L. Ratti b,c, V. Re a,c a Università degli

More information

SRAM Scaling Limit: Its Circuit & Architecture Solutions

SRAM Scaling Limit: Its Circuit & Architecture Solutions SRAM Scaling Limit: Its Circuit & Architecture Solutions Nam Sung Kim, Ph.D. Assistant Professor Department of Electrical and Computer Engineering University of Wisconsin - Madison SRAM VCC min Challenges

More information

«A 32-bit DSP Ultra Low Power accelerator»

«A 32-bit DSP Ultra Low Power accelerator» «A 32-bit DSP Ultra Low Power accelerator» E. Beigné edith.beigne@cea.fr CEA LETI MINATEC, Grenoble, France www.cea.fr Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology

More information

Single-phase DC Brushless Motor Driver IC

Single-phase DC Brushless Motor Driver IC Single-phase DC Brushless Motor Driver IC GENERAL DESCRIPTION The NJU7356 is a single-phase DC brushless motor driver IC designed for small and high power fan-motor applications. It provides a low operating

More information

Memory Structures. Ramon Canal NCD - Master MIRI. Slides based on:introduction to CMOS VLSI Design. D. Harris. NCD - Master MIRI 1

Memory Structures. Ramon Canal NCD - Master MIRI. Slides based on:introduction to CMOS VLSI Design. D. Harris. NCD - Master MIRI 1 Memory Structures Ramon Canal NCD - Master MIRI Slides based on:introduction to CMOS VLSI Design. D. Harris NCD - Master MIRI 1 Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry

More information

Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic.

Pass-Transistor Logic. Topics. NMOS-Only Logic. Pass-Transistor Logic. Resistance of Transmission Gate. Pass-Transistor Logic. Topics Transmission Gate Pass-transistor Logic 3 March 2009 1 3 March 2009 2 NMOS-Only Logic Example: AND Gate 3 March 2009 3 3 March 2009 4 Resistance of Transmission Gate XOR 3 March 2009 5 3 March 2009

More information

Semiconductor Memories

Semiconductor Memories Semiconductor Memories Semiconductor memories array capable of storing large quantities of digital information are essential to all digital systems Maximum realizable data storage capacity of a single

More information

CMOS Power Consumption

CMOS Power Consumption CMOS Power Consumption Lecture 13 18-322 Fall 2003 Textbook: [Sections 5.5 5.6 6.2 (p. 257-263) 11.7.1 ] Overview Low-power design Motivation Sources of power dissipation in CMOS Power modeling Optimization

More information

Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap

Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Silicon Memories Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

More information

CMOS Digital Circuits

CMOS Digital Circuits CMOS Digital Circuits Types of Digital Circuits Combinational The value of the outputs at any time t depends only on the combination of the values applied at the inputs at time t (the system has no memory)

More information

Class 18: Memories-DRAMs

Class 18: Memories-DRAMs Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation

More information

BiCMOS Logic Gates. University of Connecticut 224

BiCMOS Logic Gates. University of Connecticut 224 BiCMOS Logic Gates University of Connecticut 224 BiCMOS - Best of Both Worlds? CMOS circuitry exhibits very low power dissipation, but Bipolar logic achieves higher speed and current drive capability.

More information

What Does Rail-to-Rail Operation Really Mean?

What Does Rail-to-Rail Operation Really Mean? What Does Rail-to-Rail Operation Really Mean? 2004 Microchip Technology Incorporated. All Rights Reserved. What does Rail-to-Rail Operation really mean? 1 Agenda What does Rail-to-Rail output operation

More information

Yaffs NAND Flash Failure Mitigation

Yaffs NAND Flash Failure Mitigation Yaffs NAND Flash Failure Mitigation Charles Manning 2012-03-07 NAND flash is one of very few types of electronic device which are knowingly shipped with errors and are expected to generate further errors

More information

Power-Saving Techniques and Future Design of SPARC64 V/VI

Power-Saving Techniques and Future Design of SPARC64 V/VI Power-Saving Techniques and Future Design of SPARC64 V/VI V Aiichiro Inoue (Manuscript received May 31, 2007) The performance of high-end microprocessors has increased along with improvements in semiconductor

More information

Memory Design. Memory Types Memory Organization ROM design RAM design PLA design

Memory Design. Memory Types Memory Organization ROM design RAM design PLA design Memory Design Memory Types Memory Organization ROM design RAM design PLA design Adapted from J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, 2 nd ed. Copyright 2003 Prentice

More information

Compact MOSFET Model for ESD Applications*

Compact MOSFET Model for ESD Applications* Compact MOSFET Model for ESD Applications* Juin J. Liou 1 and Xiaofang Gao 2 1 Electrical and Computer Engineering Dept. University of Central Florida, Orlando, Florida 2 Modeling and Simulation Group

More information

Leakage Reduction in Nanometer SRAM cell using Power Gating V DD control technique

Leakage Reduction in Nanometer SRAM cell using Power Gating V DD control technique S. P. Singh, M. Mishra and G. Srivastava / IJECCT 2013, Vol. 3 (3) 20 Leakage Reduction in Nanometer SRAM cell using Power Gating V DD control technique Suryabhan Pratap Singh¹, Manish Mishra¹, Geetika

More information

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 14 Pass Transistor Logic Circuits - I Hello

More information

Layout Design and Simulation of CMOS Multiplexer

Layout Design and Simulation of CMOS Multiplexer 23 Layout and Simulation of CMOS Multiplexer Priti Gupta Electronics & Communication department National Institute of Teacher s Training and Research Chandigarh Rajesh Mehra Electronics & Communication

More information

CMOS, the Ideal Logic Family

CMOS, the Ideal Logic Family CMOS, the Ideal Logic Family INTRODUCTION Let s talk about the characteristics of an ideal logic family. It should dissipate no power, have zero propagation delay, controlled rise and fall times, and have

More information

Context. Faults are often modeled according two fault models: Bit Set (resp. Reset) Bit Flip

Context. Faults are often modeled according two fault models: Bit Set (resp. Reset) Bit Flip FDTC 2013 Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells Cyril Roscian, Alexandre Sarafianos, Jean-Max Dutertre, Assia Tria Secured Architecture and System Laboratory Centre Microélectronique

More information

A Power Efficient Multiplexer and Flip-Flop Design Using Modified NAND Gate

A Power Efficient Multiplexer and Flip-Flop Design Using Modified NAND Gate A Power Efficient Multiplexer and Flip-Flop Design Using Modified NAND Gate Radhika.T 1, Lakshmisree P.V 2 1 PG Scholar,M.Tech VLSI Design, t.radhika1@gmail.com,n.c.e.r.c,pampady, Thrissur,Kerala, India

More information

EEC 118 Spring 2011 Midterm

EEC 118 Spring 2011 Midterm EEC 118 Spring 2011 Midterm Rajeevan Amirtharajah Dept. of Electrical and Computer Engineering University of California, Davis May 2, 2011 This examination is closed book and closed notes. Some formulas

More information

Chip Package Resonance in Core Power Supply Structures for a High Power Microprocessor

Chip Package Resonance in Core Power Supply Structures for a High Power Microprocessor Proceedings of IPACK 0 The Pacific Rim/ASME International Electronic Packaging Technical Conference and Exhibition July 8 3, 200, Kauai, Hawaii, USA Chip Package Resonance in Core Power Supply Structures

More information

GDI Technique : A Power-Efficient Method for Digital Circuits

GDI Technique : A Power-Efficient Method for Digital Circuits GDI Technique : A Power-Efficient Method for Digital Circuits Kunal & Nidhi Kedia Department of Electronics & Telecommunication Engineering, Synergy Institute of Engineering & Technology, Dhenkanal, Odisha

More information

Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology

Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology Institute of Integrated Sensor Systems Dept. of Electrical Engineering and Information Technology Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology Benjamin LUTGEN Wintersemester

More information

Adiabatic 5T SRAM. Mamatha Samson, Satyam Mandavalli. International Symposium on Electronic System Design (ISED) :

Adiabatic 5T SRAM. Mamatha Samson, Satyam Mandavalli. International Symposium on Electronic System Design (ISED) : Adiabatic 5T SRAM by Mamatha Samson, Satyam Mandavalli in International Symposium on Electronic System Design (ISED) : 267-272 Kochi, India Report No: IIIT/TR/2011/-1 Centre for VLSI and Embeded Systems

More information

Low-Voltage Switched-OpAmp Circuits. Term Paper

Low-Voltage Switched-OpAmp Circuits. Term Paper University of Toronto Department of Electrical and Computer Engineering Low-Voltage Switched-OpAmp Circuits Analog Circuit Design I ECE1352F Term Paper University of Toronto Electronics Group Toronto,

More information

E3 239 Advanced VLSI Circuits. High-Performance SRAM Design

E3 239 Advanced VLSI Circuits. High-Performance SRAM Design E3 239 Advanced VLSI Circuits High-Performance SRAM Design Rahul Rao IBM Systems and Technology Group Topics Introduction to memory SRAM basics and bitcell array (fsher) Curnt Challenges Alternative Cell

More information

Photonic Networks for Data Centres and High Performance Computing

Photonic Networks for Data Centres and High Performance Computing Photonic Networks for Data Centres and High Performance Computing Philip Watts Department of Electronic Engineering, UCL Yury Audzevich, Nick Barrow-Williams, Robert Mullins, Simon Moore, Andrew Moore

More information

Technical Summary on Non-Volatile ROMs

Technical Summary on Non-Volatile ROMs International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869, Volume-2, Issue-6, June 2014 Technical Summary on Non-Volatile ROMs Sampa Paul Abstract In this paper, several types

More information

Lecture 12: MOS Decoders, Gate Sizing

Lecture 12: MOS Decoders, Gate Sizing Lecture 12: MOS Decoders, Gate Sizing MAH, AEN EE271 Lecture 12 1 Memory Reading W&E 8.3.1-8.3.2 - Memory Design Introduction Memories are one of the most useful VLSI building blocks. One reason for their

More information

ΔI DDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects *

ΔI DDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects * Circuits and Systems, 2011, 2, 133-138 doi:10.4236/cs.2011.23020 Published Online July 2011 (http://www.scirp.org/journal/cs) ΔI DDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation

More information

Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-1

Lecture 230 Design of Two-Stage Op Amps (3/27/10) Page 230-1 Lecture 230 Design of TwoStage Op Amps (3/27/0) Page 230 LECTURE 230 DESIGN OF TWOSTAGE OP AMPS LECTURE OUTLINE Outline Steps in Designing an Op Amp Design Procedure for a TwoStage Op Amp Design Example

More information

Memory Design. Random Access Memory. Row decoder. n bit address. 2 m+k memory cells wide. n-1:k. Column Decoder. k-1:0.

Memory Design. Random Access Memory. Row decoder. n bit address. 2 m+k memory cells wide. n-1:k. Column Decoder. k-1:0. Memory Design Random Access Memory Row decoder 2 m+k memory cells wide n-1:k k-1:0 Column Decoder n bit address Sense Amplifier m bit data word Memory Timing: Approaches Address bus Row Address Column

More information

A Bootstrapped Switch for Precise Sampling of Inputs with Signal Range Beyond Supply Voltage

A Bootstrapped Switch for Precise Sampling of Inputs with Signal Range Beyond Supply Voltage D. Aksin, M.A. Al- Shyoukh, F. Maloberti: "A Bootstrapped Switch for Precise Sampling of Inputs with Signal Range Beyond Supply Voltage"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 25,

More information

Introduction to CMOS VLSI Design. Lecture 6: Wires. David Harris

Introduction to CMOS VLSI Design. Lecture 6: Wires. David Harris Introduction to CMOS VLSI Design Lecture 6: Wires David Harris Harvey Mudd College Spring 2004 Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors

More information

Class 11: Transmission Gates, Latches

Class 11: Transmission Gates, Latches Topics: 1. Intro 2. Transmission Gate Logic Design 3. X-Gate 2-to-1 MUX 4. X-Gate XOR 5. X-Gate 8-to-1 MUX 6. X-Gate Logic Latch 7. Voltage Drop of n-ch X-Gates 8. n-ch Pass Transistors vs. CMOS X-Gates

More information

New High Speed Switch Offers Sub-50ns Switching Times

New High Speed Switch Offers Sub-50ns Switching Times New High Speed Switch Offers Sub-50ns Switching Times Application Note December AN5. Introduction An ideal CMOS analog switch would exhibit such characteristics as zero resistance when turned on, infinite

More information

11-1. Stick Diagram and Lamda Based Rules

11-1. Stick Diagram and Lamda Based Rules 11-1 Stick Diagram and Lamda Based Rules Mask Layout (Print this presentation in colour if possible, otherwise highlight colours) 11-2 Circuit coloured mask layer layout Coloured stick diagram mask representation

More information

Power Amplifier Classes Based upon Harmonic Approximation and Lumped-element Loading Networks

Power Amplifier Classes Based upon Harmonic Approximation and Lumped-element Loading Networks Power Amplifier Classes Based upon Harmonic Approximation and Lumped-element Loading Networks (Invited Paper) Ramon A. Beltran, PhD. UCSD Power Amplifier Symposium September 2014 Skyworks Solutions, Inc.

More information

DESIGN CHALLENGES OF TECHNOLOGY SCALING

DESIGN CHALLENGES OF TECHNOLOGY SCALING DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE

More information

P-channel enhancement mode MOS transistor

P-channel enhancement mode MOS transistor FEATURES SYMBOL QUICK REFERENCE DATA Very low threshold voltage s V DS = - V Fast switching Logic level compatible I D = -.47 A Subminiature surface mount g package R DS(ON). Ω (V GS =.5 V) GENERAL DESCRIPTION

More information

S6A SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD S6A69 4 SEG / 6 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD June 2 Ver Contents in this document are subject to change without notice No part of this document may be reproduced or transmitted in any form

More information

New Encoding Method for Low Power Sequential Access ROMs

New Encoding Method for Low Power Sequential Access ROMs JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.13, NO.5, OCTOBER, 2013 http://dx.doi.org/10.5573/jsts.2013.13.5.443 New Encoding Method for Low Power Sequential Access ROMs Seong-Ik Cho, Ki-Sang

More information

Principles of VLSI Design Introduction

Principles of VLSI Design Introduction Principles of VLSI Design Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition. by Neil H.E. Weste and David Harris.

More information

N-channel enhancement mode MOS transistor

N-channel enhancement mode MOS transistor FEATURES SYMBOL QUICK REFERENCE DATA Very low threshold voltage d V DS = V Fast switching Logic level compatible I D =.5 A Subminiature surface mount package R DS(ON) 5 mω (V GS =.5 V) g s V GS(TO).4 V

More information

Layout, Fabrication, and Elementary Logic Design

Layout, Fabrication, and Elementary Logic Design Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design Adapted from Weste & Harris CMOS VLSI Design Overview Implementing switches with CMOS transistors How to compute logic

More information

Chapter 10 Advanced CMOS Circuits

Chapter 10 Advanced CMOS Circuits Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in

More information

Digital Integrated Circuits Lecture 10: Wires

Digital Integrated Circuits Lecture 10: Wires Digital Integrated Circuits Lecture 10: Wires Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec10 cwliu@twins.ee.nctu.edu.tw 1 Outline Introduction

More information

Sense Amplifier for SRAM

Sense Amplifier for SRAM Sense Amplifier for SRAM Professor : Der-Chen Huang SoC Lab Outline SRAM Structure Sense Amplifier Introduction Voltage-mode Current-mode Traditional Voltage-Mode Sense Amplifier Current-Mode Sense Amplifier

More information

International Journal of Electronics and Computer Science Engineering 1482

International Journal of Electronics and Computer Science Engineering 1482 International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant

More information

FLASH TECHNOLOGY DRAM/EPROM. Flash. 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, "Memory 1996"

FLASH TECHNOLOGY DRAM/EPROM. Flash. 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, Memory 1996 10 FLASH TECHNOLOGY Overview Flash memory technology is a mix of EPROM and EEPROM technologies. The term flash was chosen because a large chunk of memory could be erased at one time. The name, therefore,

More information

CHAPTER 16 MEMORY CIRCUITS

CHAPTER 16 MEMORY CIRCUITS CHPTER 6 MEMORY CIRCUITS Chapter Outline 6. atches and Flip-Flops 6. Semiconductor Memories: Types and rchitectures 6.3 Random-ccess Memory RM Cells 6.4 Sense-mplifier and ddress Decoders 6.5 Read-Only

More information

Leakage Power Reduction Using Sleepy Stack Power Gating Technique

Leakage Power Reduction Using Sleepy Stack Power Gating Technique Leakage Power Reduction Using Sleepy Stack Power Gating Technique M.Lavanya, P.Anitha M.E Student [Applied Electronics], Dept. of ECE, Kingston Engineering College, Vellore, Tamil Nadu, India Assistant

More information

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V

MRF175GU MRF175GV The RF MOSFET Line 200/150W, 500MHz, 28V Designed for broadband commercial and military applications using push pull circuits at frequencies to 500 MHz. The high power, high gain and broadband performance of these devices makes possible solid

More information

CD4027BMS. CMOS Dual J-K Master-Slave Flip-Flop. Pinout. Features. Functional Diagram. Applications. Description. December 1992

CD4027BMS. CMOS Dual J-K Master-Slave Flip-Flop. Pinout. Features. Functional Diagram. Applications. Description. December 1992 CD7BMS December 199 CMOS Dual J-K Master-Slave Flip-Flop Features Pinout High Voltage Type (V Rating) Set - Reset Capability CD7BMS TOP VIEW Static Flip-Flop Operation - Retains State Indefinitely with

More information

Compact Modeling of Non-volatile Memory Devices. M. Sadd, R. Muralidhar and R. Rao 20 September 2004

Compact Modeling of Non-volatile Memory Devices. M. Sadd, R. Muralidhar and R. Rao 20 September 2004 Compact Modeling of Non-volatile Memory Devices M. Sadd, R. Muralidhar and R. Rao 20 September 2004 Outline Introduction to flash Capacitor sub-circuit and sense model Challenges in Thin film storage model

More information

Sequential 4-bit Adder Design Report

Sequential 4-bit Adder Design Report UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela

More information

Three Stage Push Pull Inverters Based Transimpedance Amplifier

Three Stage Push Pull Inverters Based Transimpedance Amplifier Three Stage Push Pull Inverters Based Transimpedance Amplifier Harshit Parmar 1, D.S.Ajnar 2, P.K.Jain 3 P.G. Student (Microelectronics and VLSI Design), Department of E&I, Shri G. S. Institute of Technology

More information

Power consumption is now the major technical

Power consumption is now the major technical COVER FEATURE Leakage Current: Moore s Law Meets Static Power Microprocessor design has traditionally focused on dynamic power consumption as a limiting factor in system integration. As feature sizes shrink

More information

Electrostatic Discharge (ESD)

Electrostatic Discharge (ESD) Electrostatic Discharge (ESD) ELEC 353 Electronics II Instructor: Prof. C. Saavedra What is ESD? A sudden current flow between two objects that are at different potentials ESD currents are large and of

More information

Phase-state Low Electron-number Drive Random Access Memory (PLEDM)

Phase-state Low Electron-number Drive Random Access Memory (PLEDM) TA 7.4 Phase-state Low Electron-number Drive Random Access Memory (PLEDM) Kazuo Nakazato, Kiyoo Itoh 1, Haroon Ahmed 2, Hiroshi Mizuta, Teruaki Kisu 3, Masataka Kato 4, Takeshi Sakata 1 Hitachi Cambridge

More information

Basic CMOS concepts. Computer Design and Technology Assignment 2

Basic CMOS concepts. Computer Design and Technology Assignment 2 Basic CMOS concepts We will now see the use of transistor for designing logic gates. Further down in the course we will use the same transistors to design other blocks (such as flip-flops or memories)

More information

Digital Design for Low Power Systems

Digital Design for Low Power Systems Digital Design for Low Power Systems Shekhar Borkar Intel Corp. Outline Low Power Outlook & Challenges Circuit solutions for leakage avoidance, control, & tolerance Microarchitecture for Low Power System

More information

Basics of Energy & Power Dissipation

Basics of Energy & Power Dissipation Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation

More information

Substrate Noise Coupling in Mixed-Signal Systems

Substrate Noise Coupling in Mixed-Signal Systems Substrate Noise Coupling in Mixed-Signal Systems Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester Intel Design and Technology Solutions Annual Symposium July 9-10,

More information

Low latency synchronization through speculation

Low latency synchronization through speculation Low latency synchronization through speculation D.J.Kinniment, and A.V.Yakovlev School of Electrical and Electronic and Computer Engineering, University of Newcastle, NE1 7RU, UK {David.Kinniment,Alex.Yakovlev}@ncl.ac.uk

More information

DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE

DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE http:// DESIGN AND IMPLEMENTATION OF OPTIMIZED 4:1 MUX USING ADIABATIC TECHNIQUE 1 Dikshant Kamboj, 2 Arvind Kumar, 3 Vijay Kumar 1 M.Tech (Microelectronics), 2,3 Assistant Professor, University Institute

More information

International Journal of Engineering Science Invention Research & Development; Vol. I Issue I July 2014

International Journal of Engineering Science Invention Research & Development; Vol. I Issue I July 2014 Design Analysis of XOR Gates Using CMOS & Pass Transistor Logic Pooja Singh 1, Rajesh Mehra 2 2 Research Scholar, 1 Professor, ECE Dept. NITTTR,Chandigarh Abstract-This paper compares two different logic

More information