Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 ISSN(Print) ISSN(Online) Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage Wookhyun Kwon 1, In Jun Park 2, and Changhwan Shin 2,* Abstract For highly scalable NAND flash memory applications, a compact (4F 2 /cell) nonvolatile memory architecture is proposed and investigated via threedimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions. Index Terms Flash memory cell, NAND, CMOS I. INTRODUCTION SONOS, short for silicon-oxide-nitride-oxidesilicon, is a type of nonvolatile memory that has a silicon nitride (SiN) layer located in the gate oxide. Electrons are trapped in the SiN layer and can be stored for sufficient duration for the layer to function as a Manuscript received Dec. 24, 2014; accepted Mar. 18, Samsung Electronics, Hwasung, Korea 2 School of Electrical and Computer Engineering, University of Seoul, Seoul , Korea cshin@uos.ac.kr nonvolatile memory. The concept of a charge-trapped nonvolatile SONOS cell was first introduced in the 1960s and initial commercialized devices were demonstrated in the early 1970s [1, 2]. After conventional floating-polygate flash devices were introduced in the late 1980s, the popularity of SONOS device diminished [3]. Because of the poor charge-trapping efficiency of the SiN layer and the poor retention time caused by the relatively shallow trapping energy state of the SiN layer, SONOS device cells require relatively higher operation voltages but provide shorter retention time. Now, as the conventional NAND flash technology faces scaling challenges below 20 nm, the charge-trapped flash (CTF) memory is considered again for the implementation of future NAND flash memory [4]. One example is the development of vertical three-dimensional (3D) NAND technology where CTF technology is used for making stackable array structures [5, 6]. The structure of a CTF memory imposes many restrictions on scaling of the devices because a trapping layer exists between a silicon channel and the gate material of the memory device. A CTF memory device requires the tunnel oxide of sufficient thickness to avoid read disturbance due to high pass-gate voltages, but this results in poor electrostatic integrity. Therefore, the channel length of a CTF device is maintained (by the use of a 3D stack) rather than aggressively scaled. A backside trapping structure design has been proposed for optimizing the gate oxide and the ONO stack [7]. The device in [7] has the modified silicon-oninsulator (SOI) substrate where charge is stored in a charge-trapping region underneath the thin single-crystal silicon of the channel region. Nevertheless, it is not suitable to form a NAND cell array because it cannot

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, Table 1. BCS-NVM Cell Design Parameters Parameters Quantity (Dimension) Cell size (4F 2 ) (μm 2 ) N body (= N A) (cm -3 ) T Gox T silicon Tunnel oxide Storage nitride Blocking oxide L channel W active 2 (nm) 7 (nm) 30 (Å) 100 (Å) 40 (Å) 18 (nm) 18 (nm) Fig. 1. (a) Cross-sectional view, (b) top view of BCS-NVM cells. Fig. 3. Conceptual schematic of BSC-NAND cell array. Fig. 2. Circuit schematic of a BCS-NVM cell array. avoid program disturbance problem. As a NAND-type backside trapping device, a new backside charge storage nonvolatile memory (BCS-NVM) cell design is proposed [8]. In this paper, more detailed explanations and discussions are provided. During a read operation, the neighboring gate fringing electric fields form conductive source and drain regions in-between the cells. The design parameters of the device, suitable for 18 nm technology, are summarized in Table 1. Note that the cell is essentially a back-gated thin-body transistor [i.e., fully-depleted silicon-on-insulator (FDSOI)], which means that it should be more scalable than a conventional bulk flash memory cell. Fig. 2 shows the circuit schematic of a possible BCS- NVM cell array. The circuit schematic can be realized by using the configuration of the cell array as shown in Fig. 1(b), which can achieve the most efficient cell layout area (i.e., 4F 2 ). III. CELL OPERATION II. DEVICE STRUCTURE Fig. 1(a) shows the cross-sectional view of BCS-NVM cells. Each cell consists of a thin front-gate oxide, a thin active silicon channel layer, and an underlying ONO charge-trapping dielectric stack. Unlike in the conventional SONOS structure, electrons can be stored in the nitride layer only by back-gate bias. As shown in Fig. 1(b), the direction of the front-gate is perpendicular to that of the back-gate. The perpendicularity enables each back-gate line to define an erase sector shown in Fig. 2. Note that there is no doped SD junction between cells. Fig. 3 shows a conceptual schematic of storing electrons and holes in a BSC-NAND cell array. The array bias conditions for Program, Erase, and Read operations are listed in Table 2. Electron/hole injection into the nitride layer by Fowler Nordheim (FN) tunneling is used to program/erase a cell. During a read operation, the cell current is different between the states of a cell. If electrons are stored in the nitride layer underneath the cell, they make the cell threshold voltage higher, leading only the leakage current to flow when the Read gate voltage is applied as shown in Fig. 4(a). If electrons are not stored in the nitride layer underneath the cell, the cell threshold voltage is lower,

3 288 WOOKHYUN KWON et al : HIGHLY SCALABLE NAND FLASH MEMORY CELL DESIGN EMBRACING BACKSIDE Fig. 6. Simulated BCS-NVM cell programming behavior for various back-gate bias voltages. Fig. 4. Illustration of the read operation of a BCS-NVM cell in a NAND array. (a) Programmed cell is off during Read and (b) Erased cell is on during Read. Fig. 7. Simulated BCS-NVM cell erasing behavior for various back-gate bias conditions. Fig. 5. Simulated cell current (Icell) vs. front-gate voltage (Vg) characteristics for a programmed cell and an erased cell. leading the on-state drive current to flow when the Read gate voltage is applied as shown in Fig. 4(b). In Fig. 5, the simulated transfer characteristics for a programmed cell and an erased cell are shown. Regardless of the cell state, they show a low subthreshold swing (~ 80 mv/decade) with the cell exhibiting a high on/off current ratio (~ 107). In an erased cell, the inversion layer would adversely affect the performance of a cell because it has a resistance. However, this is not a problem in this cell because the series resistance of the inversion layer source/drain regions in-between the cells is sufficiently low to be accepted when the distance between the gates is very small (e.g., 20 nm or shorter) [9]. The maximum threshold voltage shift that can be achieved is determined by material parameters of the silicon band energy band gap (~ 1.12 ev) and gate work functions [10]. Figs. 6 and Figs. 7 show the simulated programming and erasing behaviors. The relatively large capacitive coupling between the back-gate and the channel enables this device to be operated under the operating voltages (~ 10 V), which are lower than those typically used for a conventional NAND flash memory. IV. CHARGE DEPLETION METHOD A NAND cell array should be immune to cell disturbance during programming. In order to avoid the disturbance, an innovative charge depletion approach is proposed as shown in Fig. 8. During programming, -2 V, 0 V, and 12 V is applied to WL, WL program, and backgate electrodes, respectively (as shown in Table 2). Because of the negative voltage applied to WL, the electrons beneath the WL electrode are depleted as shown in Fig. 9(a). A few electrons under the WL electrode can tunnel through the tunnel oxide owing to

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, Fig. 8. Schematic of selective programming operation in NAND array. Table 2. Array Biases for Program/Erase/Read of the Cell Addressed by WL0 and BL0/BGL0 Program Erase Read WL0 0.0 V 0.0 V 0.0 V BGL V V 0.0 V BL0 0.0 V 0.0 V 1.0 V WL1-2.0 V 0.0 V 1.8 V BGL1 0.0 V 0.0 V 0.0 V BL1 0.0 V 0.0 V 0.0 V DSL 0.0 V 0.0 V 1.8 V SSL 0.0 V 0.0 V 1.8 V CS 0.0 V 0.0 V 0.0 V Time 2 ms 1 ms < 10 μs Fig. 10. Simulated programming disturbance behavior of an unselected cell. The indicated disturbance time (1 ms) is the time required to program a cell in the same sector; same programming voltage (+ 12 V) is applied on the back-gate. Fig. 11. Simulated programming disturbance behavior of an unselected cell having a doped S/D junction; the peak concentration in the source/drain is cm -3. The program voltage of 12 V is applied on the back gate and a negative bias of -2V is applied on the front gate to avoid program operation of an unselected cell. Fig. 9. Contour plots during programming operation: (a) mobile electron density and (b) trapped electron density. the depletion, and can be injected into the underlying ONO layer as shown in the left part of Fig. 9(b). On the other hand, electrons under the other side (i.e., under the WL program electrode) are not pushed out because there is no electrical force from the top gate electrode. Thus, more electrons can tunnel through the oxide so that they are trapped in the underlying ONO layer as shown in the right-hand side of Fig. 9(b). Fig. 10 shows the simulated program-disturbance characteristics of unselected cells along the same back-gate line. The charge depletion method depends strongly on doping concentration. To push out electrons underneath non-selected cells, the silicon region has to be fully depleted. If metallurgical junctions are formed by source/drain (S/D) doping, electrons in the gate overlap region cannot be fully depleted with negative gate bias. Thus, the non-selected cell suffers severe program disturbance as shown in Fig. 11. In Fig. 12, subthreshold slopes of the doped S/D junction structure show poor swings comparing those of the non-doped BCS-NVM cell structure because electrically induced virtual junction of the BCS-NVM cell is thinner than that of the doped S/D junction device. The steep subthreshold slope is beneficial for lowvoltage operation.

5 290 WOOKHYUN KWON et al : HIGHLY SCALABLE NAND FLASH MEMORY CELL DESIGN EMBRACING BACKSIDE Fig. 12. Simulated transfer characteristics of a cell current having the peak concentration of dopant of cm -3 in the source/drain with different threshold voltages. The threshold voltages are obtained after various back-gate biases with a 2-ms pulse. V. CONCLUSION In this study, a backside charge storage memory cell is investigated for use in highly scalable NAND flash memory. In order not to program the unwanted cell, a charge depletion approach is proposed for the device. An acceptably large read current (~ 10 μa) for high-speed operation is achieved in an 18 nm cell of area μm 2. The thin-body structure was found to be superior to a bulk structure in terms of electrostatic integrity and enabled to be scaled down below 20 nm gate length. ACKNOWLEDGMENTS This work is supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2014R1A2A1A ). REFERENCES [1] H. A. R. Wegner, A. J. Lincoln, H. C. Pao, M. R. O Connel, R. E. Oleksiak, and H. Lawrence, The variable threshold transistor, a new electricallyalterable, non-destructive read-only storage device, in IEDM Tech. Dig., vol. 13, pp. 70, [2] P. C. Y. Chen, Threshold-alterable Si-gate MOS devices, IEEE Trans. on Electron Devices, vol. 24, no. 5, pp , May [3] 2012 isuppli annual report. [4] M. White, On the Go with SONOS, IEEE Circuits and Device Magazine, vol. 16, no. 4, pp , Jul [5] H. Tanaka et al., Bit cost scalable technology with punch and plug process for ultra high density flash memory, in Proc. Symp. VLSI Technol., pp , Jun [6] J. Jang et al., Vertical cell array using TCAT technology for ultra-high density NAND flash memory, in Proc. Symp. VLSI Technol., pp , Jun [7] H. Silva and S. Tiwari, A nanoscale memory and transistor using backside trapping, IEEE Trans. on Nanotechnology, vol. 3, no. 2, pp , Jun [8] W. Kwon and T. King Liu, Compact NAND flash memory cell design utilizing backside charge storage, in IEEE Silicon Nanoelectronics Workshop, Jun [9] C. H. Lee, J. Choi, Y. Park, C. Kang, B. Choi, H. Kim, H. Oh, and W. Lee, Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure, in Proc. Symp. VLSI Technol., pp , Jun [10] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, Wookhyun Kwon received his M.S. degree in electrical engineering in 1997 from Pohang University of Science and Technology (POSTECH), Pohang, Korea, and Ph. D. degree in electrical engineering and computer science in 2013 from University of California at Berkeley, Berkeley, California, USA. In 2003, he joined the Samsung Electronics Company, Ltd., Giheung, Korea, where he has been engaged in the research and development of high-density flash memories. He is currently the principal engineer in semiconductor R&D center of Samsung Electronics, Ltd., Hwasung, Korea, where he is in charge of the development of next-generation logic transistor technology. He has published articles about memory technologies and mechanical nonvolatile memories. His current research interests are in sub-10 nm transistor technology, FinFET structure reliability, and powerperformance analysis for technology benchmarking.

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, In Jun Park was born in Incheon, Korea, in He received his B.S. and M.S. degree in 2013 and 2015 from the School of Electrical and Computer Engineering, University of Seoul, Seoul, Korea. His current research interests include vacuumchannel transistors and random variation analysis in CMOS technology. Changhwan Shin received his B.S. degree (top honors) in Electrical Engineering in 2006 from Korea University, Seoul, Korea, and the Ph.D. degree in Electrical Engineering and Computer Sciences in 2011 from the University of California, Berkeley. His current research interests include advanced CMOS device designs and their applications to variation-robust System-On-Chip (SoC) memory and logic devices, as well as post-silicon technology. Prof. Shin was the recipient of a fellowship from the Korea Foundation for Advanced Studies (KFAS) in 2004, the General Electric Foundation Scholar Leaders Award in 2005, the Best Paper Award and the Best Student Paper Award at the IEEE International SOI Conference in 2009, and the Best Paper Award at the European Solid State Device Research Conference (ESSDERC) in He has been serving on technical committees for the IEEE International SOI conference (now, IEEE SOI-3D-Subthreshold (S3S) conference) and the European Solid State Device Research Conference (ESSDERC) since He is now serving as Vice Dean, College of Engineering, University of Seoul.