Evaluating Embedded Non-Volatile Memory for 65nm and Beyond

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1 Evaluating Embedded Non-Volatile Memory for 65nm and Beyond Wlodek Kurjanowicz DesignCon 2008 Sidense Corp 2008

2 Agenda Introduction: Why Embedded NVM? Embedded Memory Landscape Antifuse Memory evolution 1.5T cell 1T cell 1T/1.5T comparison Scaling Challenges Summary 2

3 Why Embedded NVM? Three Basic Rules in Real Estate Investing: Location (know your Budget) Location (choose good location) Location (have a plan in place) Same rules apply to Silicon Real Estate: Cost effective NVM for on-chip trimming and repair Secure NVM for on-chip encryption keys Reliable and portable NVM for on-chip firmware and software updates 3

4 130nm Memory Bit-Cell Comparison 2um POLY F=1/2 DRAM Pitch [ITRS Roadmap] 5um 0.13um SRAM DRAM efuse IBM System Z9 PGM: 10-15mA / bit 50µm nmos switch READ: <0.5mA / bit Floating Gate Logic NVM Six HV (3.3V) Transistors /bit 6T SRAM 140F 2 +2 Masks 1T1C DRAM 12-30F 2 +3/5 Masks NOR Flash 10F 2 +6/8 Masks 1T Anti- Fuse >10F 2 Mask ROM <10F 2 Know Your Budget! Size Does Matter! 4

5 Embedded Memory Landscape 2um POLY 5um 0.13um SRAM DRAM 6T SRAM 1T1C DRAM NOR Flash 1T Anti- Fuse Mask ROM Floating Gate Logic NVM efuse Security and Field Programmability 5

6 Secure Embedded NVM Landscape NOR Flash +6 / 8 Masks 1T Anti- Fuse Floating Gate Logic NVM 3.3V Transistors ECC needed for retention Reliability and Portability Across Fabs and Process Nodes 6

7 What is an Antifuse A structure alterable to a conductive state An electronic device that changes state from not conducting to conducting or from higher resistance to lower resistance in response to electrical stress (programming voltage or current). MOS capacitor is an excellent antifuse Programmed by gate oxide rupture Exact mechanism still not well understood Gate leakage is in order of pa or na Oxide breaks down at 5-8V Gate current increases >10,000x 7

8 MOS Antifuse Memory Evolution 1969, Semiconductor Antifuse Inter-Metal Cap blown at the row/column cross point 1979, MOS Antifuse Cap shorted to GND when gate oxide blown at the tip of the groove 1982, Dual Oxide 1.5T MOS Antifuse Gate-Drain shorted in the overlap area, avalanche enhanced 1985, MOS Cap Antifuse 1986, ONO Antifuse 8

9 1T1C (1.5T) Planar DRAM Antifuse 1T Thick Gate Oxide Access MOS 1C Thin Gate Oxide Storage MOS PL0 WL0 PL1 WL1 BL3 BL2 BL1 BL0 channel 9

10 Improved 2-Terminal 1.5T Antifuse 1T Thick Gate Oxide Access MOS 1C Thin Gate Oxide Storage MOS WL0 WL1 BL3 BL2 BL1 BL0 channel 10

11 Programming the Antifuse VPP Voltage Level VPP High enough to break Thin Gate Oxide 0V Too low to break Thick Gate Oxide Permanent Structural Change requires Energy (=V*I*t) 11

12 Oxide Rupture Mechanism VPP More Tunneling Current Tmax? Yes Rupture No Oxide melts Need V, I and time to avoid Soft Breakdown of gate oxide New Traps Soft Breakdown 2nm Inversion Channel n+ Poly Gate Communicating traps P- Tunneling: Fowler- Nordheim Direct Trap Assisted +6V 0V High Electric Field 30MV/cm 12

13 Nano-scale Crystallization Oxide melts in the breakdown area 100µA/100nm 2 =1A/µm 2 =1,000,000A/mm 2 N-type Silicon filament is grown A nano-scale diode-connected NMOS transistor is born Antifuse programming results in permanent STRUCTURAL CHANGE n- - +6V n+ Poly Gate n n nm High Current Density 1A/µm 2 P- p 0V 13

14 Where the Gate Oxide Breaks? 1. Channel 2. Transition Area (Halo or Pocket Implant) 3. LDD 3 cell characteristics! 3 Program Areas Poly Gate Poly Gate N+ LDD P- N+ LDD P- Channel Isol Leakage Control Implantation 14

15 Sidense Split-Channel 1T-Fuse Cell Diffusion area removed Portable between fabs Programs always in channel area Permanent structural change Consistent cell characteristic Reliability = integrity of un-programmed gate oxide Yield = integrity of un-programmed gate oxide Programmability = presence of gate oxide and BL contact 15

16 1.5T / 1T Cell Current Comparison T / 1T Cell Current Histogram Comparison 130nm Low Leakage Process 1.5T 1T 1.5T- High Current Tail (LDD Region) 1000 Number of Bits # of Bits T- High Vt Tail (Halo Region) Micro Amps Cell Current µa 1T- No Tail (Channel Region) 16

17 1.5T / 1T Cell Area Comparison Legend: Bit Line Contact Poly Core Oxide Poly Gate IO Oxide Poly Gate Diffusion Cell Boundary PL FLOATING NODE SL WL WL WL WL BL BL BL BL High Density Mask ROM (1T) 3 terminals Sidense 1T OTP (0.5T effective) 2 terminals 1.5T OTP 2 terminals Generic 2T OTP 3 terminals 17

18 Antifuse Yield and Reliability 1.5T Antifuse Yield and reliability concern Tail bits problem Can t differentiate between slow and softly programmed bits Need higher read voltage and longer time, which compromise retention Poor portability Split-Channel 1T Antifuse Good yield and reliability No tail No softly programmed bits Fast access Improved retention Good portability 18

19 Antifuse Cell Sense Margin % Cells % Retention T est, Lot #S5, 250C (64 Macros x 1kbit) UnPGM_0h UnPGM-240h UnPGM_400h PGM_0h PGM_240h PGM_400h >1,000x margin between programmed and un-programmed cells Sense window improves with time Cell Current Cell Current (relative values) Un-programmed Cells Programmed Cells 19

20 Typical Antifuse HTOL Results No fails, 80 devices (2.7Mbit each) 1000h 1.25xVcc, 125C Example of cell current distribution Two chips, 160 macros each, 5.4Mbit total Read Point Total (hrs) T0 T1 180 T2 400 T3 600 T Cell Current Cell Current 20

21 Challenges Beyond 65nm Gate dielectric integrity (defect density) Minimize gate perimeter and area, 1T cell advantage Increased leakage Use IO devices IO / Core voltage ratio Need headroom to pass programming voltage Increased process variability 1.5T cell concern Power density on-chip Not a concern for antifuse New gate materials New opportunities? 21

22 NVM for 65nm and Beyond Split-channel 1T-Fuse: No extra masks or process steps Programmed state is permanent Smallest embedded OTP cell Improved yield and reliability Tight cell current distribution No breakdown to LDD, Pocket or Halo implantation Portable and scalable with CMOS Logic No dependence on Source and Drain engineering Proven in 180nm - 65nm, portable to 40nm and below 22

23 Thank You 23

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