Adder.PPT(10/1/2009) 5.1. Lecture 13. Adder Circuits

Transcription

1 Adder.T(//29) 5. Lecture 3 Adder ircuits Objectives Understand how to add both signed and unsigned numbers Appreciate how the delay of an adder circuit depends on the data values that are being added together

2 Adder.T(//29) 5.2 Full Adder + Output is a 2-bit number counting how many inputs are high ymmetric function of the inputs elf-dual: Invert all inputs invert all outputs If k inputs high initially then 3 k high when inverted Inverting all bits of an n-bit number make x 2 n x Note: = ( ) = ( )

3 Adder.T(//29) 5.3 Full Adder ircuit 9-gate full-adder NAND implementation (do not memorize) ropagation delays: From To Delay or, 3, or 2 omplexity: 25 gate inputs 5 transistors but use of omplexity: 25 gate inputs 5 transistors but use of complex gates can reduce this somewhat.

4 Adder.T(//29) 5.4 N-bit adder We can make an adder of arbitrary size by cascading full adder sections: The main reason for using 2 s complement notation for signed numbers is that: igned and unsigned numbers can use identical circuitry

5 Adder.T(//29) 5.5 Adder ize election The number of bits needed in an adder is determined by the range of values that can be taken by its output. If we add two 4-bit numbers, the answer can be in the range: to 3 for unsigned numbers -6 to +4 for signed numbers In both cases we need a 5-bit adder to avoid any possibility of overflow: ? ? We need to expand the input numbers to 5 bits. How do we do this?

6 Adder.T(//29) 5.6 Unsigned numbers Expanding Binary Numbers Expand an unsigned number by adding the appropriate number of s at the MB end: 5 3 igned numbers Expand a signed number by duplicating the MB the appropriate number of times: 5 3 This is known as sign extension Unsigned hrinking Binary Numbers an delete any number of bits from the MB end so long as they are all s. igned an delete any number of bits from the MB end so long as they are all the same as the MB that remains.

7 Adder.T(//29) 5.7 Adding Unsigned Numbers To avoid overflow, we use a 5-bit adder: The MB stage is performing the addition: Thus 4 always equals 3 and 4 always equals We can use a 4-bit adder with 3 as an answer bit.

8 Adder.T(//29) 5.8 Adding igned Numbers To avoid overflow, we use a 5-bit adder: This is different from the unsigned case because 4 and 4 are no longer constants. We cannot simplify this circuit by removing the MB stage. If and have different signs then 4 will not equal 3. e.g. =, = Unsigned +=, igned += ome minor simplifications are possible: If the 4 output is not required, the circuitry that generates it can be removed. 4 can be generated directly from 3, 3 and 3 which reduces the circuitry needed for the last stage.

9 Adder.T(//29) 5.9 Adder ropagation Delay Delays within each stage (in gate delays):,, = 3,, = 2 Worst-case delay is: 2 3 = = 9 Note:Wealsohave 3 = 9 and 3 = 9 For an N-bit adder, the worst delay is (N ) = 2N+ Example of worst case delay: Initially: 3:=, 3:= 4:= hange to: 3:=, 3:= 4:=

10 Adder.T(//29) 5. Delays are Data-Dependent To determine the delay of a circuit, we need to specify:. The circuit 2. The initial value of all the inputs 3. Which of the inputs changes Example: What is the propagation delay A? A Y X B Z Answer (B=): Initially: A=, B= X=, Y=, Z=, = Then: A Y 2 gate delays Answer 2 (B=): Initially: A=, B= X=, Y=, Z=, = Then: A X Z 3 gate delays

11 Adder.T(//29) 5. Worst-ase Delays We are normally interested only in the worst-case delay from a change in any input to any of the outputs. The worst-case delay determines the maximum clock speed in a synchronous circuit: LOK W D X Logic Y D Z LOK W X Y Z time tp tp+tg T tp + tg + ts < T ince the clock speed must be chosen to ensure that the circuit always works, it is only the worst-case logic delay that matters.

12 Adder.T(//29) 5.2 uiz. In an full adder, why is it normally more important to reduce the delay from to than to reduce the delay from to? 2. How many bits are required to represent the number A+B if A and B are(a)8-bit unsigned numbers or alternatively (b) 8-bit signed numbers. 3. How do you convert a 4-bit signed number into an 8- bit signed number? 4. How do you convert a 4-bit unsigned number into an 8-bit signed number? 5. How is it possible for the propagation delay of a circuit from an input to an output to depend on the value of the other inputs?

13 Adder.T(//29) 5.3 Lecture 4 Fast Adder ircuits () Objectives Understand how the propagation delay of an adder can be reduced by inverting alternate bits. Understand how the propagation delay of an adder can be reduced still further by means of carry lookahead.

14 Adder.T(//29) 5.4 tandard N-bit Adder Delay of standard N-bit adder = 2N Delay of carry path within each full adder = 2 arry path consists of three 2-input + one 3-input NANDs

15 Adder.T(//29) 5.5 Faster Adder ircuits: Because a full-adder is self-dual, it will still work if for alternate stages we invert both the inputs and the outputs: Full Adder Now consider only the arry signals: a 2 2 b 2 c Adder tage Adder tage Adder tage 2 By merging the shaded gates we can reduce the delay to one gate per adder stage.

16 Adder.T(//29) 5.6 Fast Adder ircuits: (part 2) a b c a b a b c a b c c We can merge the 3-NAND and inverter into the final column of gates as shown; this gives one delay per stage: 2 2 a b c a b c 2a 2b 2c Adder tage Adder tage Adder tage 2 The signals a, b, c form an AND-bundle: is true only if all of them are high. We don t need the signal directly so the shaded gate can be omitted.

17 Adder.T(//29) 5.7 Fast Adder ircuits: (part 3) Even stages: Delays: a,b,c Oa,b,c,, 3,, 3 gate inputs 6 transistors Odd stages: Delays:, 5, 2 4 a,b,c Oa,b,c 33 gate inputs 66 transistors Bundles are denoted by a single wire with a / through it. 22% more transistors but twice as fast.

18 Adder.T(//29) 5.8 Fast Adder ircuits: (part 4) For an N-bit adder we alternate the two modules (with a normalish first stage): Worst case delay is:!!2 3 = 7 gate delays Note that: Delay to 4 is shorter than delay to 3 Delay from is the same as delay from Worst-case example: Initially: 3:=,, 3:=, then Delay for N-bit adder (N even) is N+3 (compare with 2N+ for original circuit)

19 Adder.T(//29) 5.9 arry Lookahead () For each bit of an N-bit adder we get a carry out (O=) if two or more of,, are equal to. There are three possibilities:,=: = always arry Inhibit,= or : = arry ropagate,=: = always arry Generate We define three signals: G = arry Generate = arry ropagate G = + arry Generate or ropagate We get a carry out from a bit position either if that bit generates a carry (G=) or else if it propagates the carry and there is a carry in from the previous bit ( = ): = G + ince G = G +, an alternate expression is: = G + G The second expression is usually used since + is easier and faster to generate than.

20 Adder.T(//29) 5.2 arry Lookahead (2) onsider all the ways in which we get a carry out of bit position 3: ) Bit 3 generates a carry:??? +??? 2) Bit 2 generates a carry and?? bit 3 propagates it. +?? 3) Bit generates a carry and? bit 2 propagates it and +? bit 3 propagates it. 4) Bit generates a carry and bit propagates it and + bit 2 propagates it and bit 3 propagates p it. 5) The input is high and bits,,2 and 3 all propagate the carry. + + Thus 3 = G3 + 3 G G G+3 2 As before, we can use Gn in place of n.

21 Adder.T(//29) 5.2 arry Lookahead (3) Each stage must now generate and G instead of : G G G G2 G G G G G G G G G2 2 G 3 G3 G3 Logic Logic Logic To later stages =G +G = G + G G + G G 2 = G 2 + G 2 G + G 2 G G + G 2 G G Worst-case propagation delay: G = gate delay (G = ) G 2 = 2 gate delays (see above expression) 2 3 = 3 gate delays (from full adder circuit) Total = 6 gate delays (independent of adder length)

22 Adder.T(//29) 5.22 arry Lookahead (4) arry lookahead circuit complexity for N-bit adder: Expression for n involves n+2 product terms each containing an average of ½(n+3) input signals. Direct implementation of equations for all N carry signals involves approx N 3 /3 transistors. N = 64 N 3 /3 = 9, By using a complex MO gate, we can actually generate n using only 4n+6 transistors so all N signals require approx 2N 2 transistors. N = 64 2N 2 = 8, Actual gain is not as great as this because for large n, the expression for n is too big to use a single gate., G and G must drive N logic blocks. For large N we must use a chain of buffers to reduce delay: G To 8 logic blocks The circuit delay is thus not quite independent of N.

23 Adder.T(//29) 5.23 uiz. What does it mean to say that a full-adder is self-dual? 2. How does placing an inverter between each stage of a multi-bit adder allow the merging of gates in consecutive stages? 3. In a 4-bit adder, give an example of a propagation delay that increases when alternate bits are inverted. 4. Why is a carry-lookahead adder generally implemented using G rather than outputs?

24 Adder.T(//29) 5.24 Lecture 5 Fast Adder ircuits (2) Objectives Understand the carry skip technique for reducing the propagation delay of an adder circuit. Understand how the carry save technique can be used when adding together several numbers. ummary o Far: ascading full adders: 2N+ gate delays, 5N transistors Use self-duality to invert odd-numbered stages: N+3 gate delays, 6N transistors arry lookahead: 6 gate delays, between ee 2N 2 and.3n 3 transistors ta sstos

25 Adder.T(//29) 5.25 onsider a 2-bit adder: arry kip (), 2,2 4,4 6,6 8,8,, 3,3 5,5 7,7 9,9, The worst-case delay path is from to. In carry skip, we speed up this path by allowing the carry signal to skip over several adder stages at a time:, 2,2 4,4 6,6 8,8,, 3,3 5,5 7,7 9,9,

26 Adder.T(//29) 5.26 arry kip (2) onsider our fast adder circuit without carry lookahead (but using alternate-bit inversion): There are two possible sorts of addition sum: All bits propagate p the carry 3 = : 3 = 4 gate delays At least one bit doesn t propagate the carry 3 is completely independent of : 3 = gate delays

27 Adder.T(//29) 5.27 arry kip (3) We speed up 3 by detecting when all bits propagate the carry and using a multiplexer to allow to skip all the way to 3: MUX G K 3X K 3X 2 3X 3X 3X alculate arry ropagate ( = ) for each bit. all this 2 gate delays since XOR gates are slow. K= ifall bits propagate the carry. ase : All bits propagate the carry!3x = gate delay (via multiplexer) ase 2: At least one bit inhibits or propagates the carry does not affect 3 Longest delays to!3x and 3:!3X = 5 (via either! or K) 3 = 7

28 Adder.T(//29) 5.28 Multiplexer Details arry kip (4) K 3 MUX G 3X K!3X!3! K 3 3 3X We merge both AND gates: the 3-AND gate merges into the following NAND the 2-AND gate merges into the next adder stage K 3 3X!3X now equals gate delay.

29 Adder.T(//29) 5.29 arry kip (5) ombine 4 blocks to make a 6-bit adder: 3: 3: 3: 3: 3: 3: 7:4 7:4 3: 3: 3: 7:4 :8 :8 3: 3: 3: :8 5:2 5:2 3: 3: 3: 5:2 3X 3 3X 7 3X 3X Worst-case delay is:!3 7! 5 = 4 gate delays Each additional block of 4 bits gives a delay of only gate delay: this corresponds to ¼ gate delay per bit. For an N-bit adder we have a delay of ¼N+. We can reduce this still further by having larger super-blocks. arry circuit delays: imple 2N+ Bit-inversion N+3 arry kip ¼N+ arry Lookahead 6 but lots of circuitry and high gate fanout more delay

30 Adder.T(//29) 5.3 Adding lots of numbers In multiplication circuits and digital filters we need to add lots of numbers together. uppose we want to add together five four-bit unsigned numbers: V, W, X, Y and Z. V3: W3: X3: Y3: Z3: D E F If we use carry-lookahead adders, each stage will have 6 gate delays. Total delay to add together K values will be (K ) 6. Thus K=6 gives a delay of 9 gate delays.

31 Adder.T(//29) 5.3 Addition Tree In practice we use a tree arrangement of adders: Number of values, K log 2 (K) Each column of adders adds a delay of 6 and halves the number of values needing to be added together. Equivalently, each column of adders reduces log 2 K by one. Hence the total delay is is log 2 K 6 giving a delay of 24 to add together 6 values. The total number of adders required is still K as before.

32 Adder.T(//29) 5.32 arry-ave Adder Take a normal 4-bit adder but don t connect up the carrys: R R R2 2 R3 3 3 We have ++R = 2 + E.g. =9, =2, R=3 gives =3, =8 We call this a carry-save adder: it reduces the addition of 3 numbers to the addition of 2 numbers. The propagation delay is 3 gates regardless of the number of bits. The amount of circuitry is much less than a carry-lookahead adder. : : R: : : _ R The circuit reduces log 2 K by.585 (from.585 to.) for a delay of 3. The overall delay we can expect is therefore log 2 K 3/.585 = log 2 K 5.3. This is better than carry lookahead for less circuitry.

33 Adder.T(//29) 5.33 arry ave Example We will calculate: = 52 A G B H R 2 D I E J F R 2 R L K 2 R N M 2 X A: B: : G: H: G: 2H: I: K: L: M: 2N: X: D: E: F: I: J: _ K: 2L: 2J: M: N: Notes:. 2 requires no logic: just connect wires appropriately 2. No logic required for adder columns with only input 3. All adders are actually only 4 bits wide 4. Final addition M+2N requires a proper adder

34 Adder.T(//29) 5.34 arry-ave Tree We can construct a tree to add sixteen values together: Number of values, K log 2 (K) Delay Delay/log 2 (K) The final stage must be a normal adder because we need to obtain a single output. The delay is the same as for a conventional lookahead-adder tree but uses much less circuitry. The irregularity of the tree causes a reduction in efficiency but this is relatively small (and becomes even smaller for large K). Inverting alternate stages will speed up both tree circuits still further but requires more circuitry.

35 Adder.T(//29) 5.35 Merry hristmas The End

36 Adder.T(//29) 5.36 uiz. Ina4bit 4-bit adder, how can you tell from :3 and :3 whether or not 3 is dependent on? 2. A multiplexer normally has 2 gate delays from its data inputs to its output. How is this reduced to gate delay in the carry skip circuit? 3. If five 4-bit numbers are added together, how many bits are needed to represent the result?