Two-level logic using NAND gates

Transcription

1 CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Two-level logic using NND gates Replace minterm ND gates with NND gates Place compensating inversion at inputs of OR gate OR gate with inverted inputs is a NND gate de Morgan s: + B = ( B) Two-level NND-NND network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed 2 1

2 Two-level logic using NND and NOR gates NND-NND and NOR-NOR networks de Morgan s law: ( + B) = B ( B) = + B written differently: + B = ( B ) ( B) = ( + B ) 3 Conversion between forms Introduce "bubbles - inversions conservation of inversions do not alter logic function B Z C D 4 2

3 Conversion between forms Example: map ND/OR network to NOR/NOR network B C D Z 5 Multiple-Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c, G = ab + bc Option 1: Separate circuits Option 2: Shared gates 6 3

4 Multiple-Output Example: BCD to 7-Segment Converter a f b g e c d abcdefg = (a) a = w x y z + w x yz + w x yz + w xy z + w xyz + w xyz + wx y z + wx y z b = w x y z + w x y z + w x yz + w x yz + w xy z + w xyz + wx y z + wx y z (b) 7 Multi-level logic x = D F + E F + B D F + B E F + C D F + C E F + G reduced sum-of-products form already simplified 6 x 3-input ND gates + 1 x 7-input OR gate 25 wires (19 literals plus 6 internal wires) 8 4

5 Non-Ideal Gate Behavior Delay a F a F Time Real gates don t respond immediately to input changes Rise/fall time Delay Pulse width 9 Momentary changes in outputs Can be useful pulse shaping circuits Can be a problem incorrect circuit operation (glitches/hazards) Example: pulse shaping circuit = 0 delays matter B C D F D remains high for three gate delays after changes from low to high F is not always 0 pulse 3 gate-delays wide 10 5

6 Hazards Glitch unwanted pulse on the output Circuit with a potential for a glitch has a hazard Three types: Static-0 : output should be 0 but has a 1 glitch Static-1 : output should be 1 but has a 0 glitch Dynamic: transition 0->1 or 1->0 with a glitch 11 Eliminating Hazards Example F(,B,C,D)=Σm(1,3,5,7,8,9,12,13) Test two single bit input transitions: > > 0101 C Z C B D D 12 6

7 CSE140: Components and Design Techniques for Digital Systems Regular logic implementation Tajana Simunic Rosing 13 ND-OR-invert gates OI function: three stages of logic ND, OR, Invert multiple gates "packaged" as a single circuit block logical concept possible implementation B C D Z B C D Z ND OR Invert NND NND Invert 2x2 OI gate symbol & & + 3x2 OI gate symbol & &

8 Conversion to OI forms General procedure to place in OI form compute the complement of the function in sum-of-products form by grouping the 0s in the Karnaugh map Example: XOR implementation xor B = B + B 15 Programmable logic arrays Pre-fabricated building block of many ND/OR gates "personalized" by making/breaking connections among the gates programmable array block diagram for sum of products form inputs ND array product terms OR array outputs 16 8

9 Enabling concept Shared product terms among outputs 17 Before & after programming Two different technologies: fuse (normally connected, break unwanted ones) anti-fuse (normally disconnected, make wanted connections) B C B B'C C' B'C' Before F0 F1 F2 F3 fter 18 9

10 Programmable logic array example Multiple functions of, B, C F1 = B C F2 = + B + C F3 = ' B' C' F4 = ' + B' + C' F5 = xor B xor C F6 = xnor B xnor C B C F1F2F3F4F5F B C full decoder as for memory address bits stored in memory F1 F2 F3 F4 F5 F6 'B'C' 'B'C 'BC' 'BC B'C' B'C BC' BC 19 PLs and PLs Programmable logic array (PL) what we've seen so far unconstrained fully-general ND and OR arrays Programmable array logic (PL) constrained topology of the OR array innovation by Monolithic Memories faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product terms 20 10

11 Example Map the following functions to the PL below: W = B + C + BC X = BC + B + B Y = BC + BC + B C B C W X Y 21 Read-only memories Two dimensional array of 1s and 0s entry (row) is called a "word" width of row = word-size index is called an "address" address is input selected word is output n word lines decoder i j word[i] = 0011 word[j] = 1010 internal organization 0 0 n-1 ddress bit lines (normally 1; set to 0 by a switch) 22 11

12 ROM structure Similar to a PL structure but with a fully decoded ND array completely flexible OR array (unlike PL) n address lines inputs decoder 2 n word lines memory array (2 n words by m bits) outputs m data lines 23 Regular logic structures for two-level logic ROM full ND plane, general OR plane cheap (high-volume component) can implement any function of n inputs medium speed PL programmable ND plane, fixed OR plane intermediate cost can implement functions limited by number of terms high speed (only one programmable plane that is much smaller than ROM's decoder) PL programmable ND and OR planes most expensive (most complex in design, need more sophisticated tools) can implement any function up to a product term limit slow (two programmable planes) 24 12

13 CSE140: Components and Design Techniques for Digital Systems Muxes and demuxes Tajana Simunic Rosing 25 Multiplexor (Mux) Mux routes one of its N data inputs to its one output, based on binary value of select inputs 4 input mux needs 2 select inputs to indicate which input to route through 8 input mux 3 select inputs N inputs log 2 (N) selects 26 13

14 Mux Internal Design 2 1 i0 d i1 2x1 mux i0 i d i0 i d 27 Muxes Commonly Together -- N-bit Mux a3 b3 a2 b2 a1 b1 a0 b0 2 1 i0 d i1 2 1 i0 d i1 2 1 i0 d i1 i0 2 1 d i1 B 4 4 I0 I1 4-bit 2x1 D 4 C Simplifying notation: 4 C is short for c3 c2 c1 c0 Ex: Two 4-bit inputs, (a3 a2 a1 a0), and B (b3 b2 b1 b0) 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between or B 28 14

15 Multiplexers/selectors (cont'd) 2:1 mux: Z = 'I 0 + I 1 4:1 mux: Z = 'B'I 0 + 'BI 1 + B'I 2 + BI 3 8:1 mux: Z = 'B'C'I 0 + 'B'CI 1 + 'BC'I 2 + 'BCI 3 + B'C'I 4 + B'CI 5 + BC'I 6 + BCI 7 In general: Z = Σ 2 n -1(m k I k ) I0 I1 2:1 mux Z k=0 in minterm shorthand form for a 2 n :1 Mux I0 I1 I2 I3 4:1 mux B Z I0 I1 I2 I3 I4 I5 I6 I7 8:1 mux B C Z 29 N-bit Mux Example Four possible display items Temperature (T), verage miles-per-gallon (), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide Choose which to display using two inputs x and y Use 8-bit 4x1 mux 30 15

16 Multiplexers as general-purpose logic 2 n-1 :1 multiplexer can implement any function of n variables with n-1 variables used as control inputs and the data inputs tied to the last variable or its complement Example: F(,B,C) = m0 + m2 + m6 + m7 31 Demultiplexers/decoders Decoders/demultiplexers: general concept single data input, n control inputs, 2 n outputs control inputs (called selects (S)) represent binary index of output to which the input is connected data input usually called enable (G) 1:2 Decoder: O0 = G S O1 = G S 2:4 Decoder: O0 = G S1 S0 O1 = G S1 S0 O2 = G S1 S0 O3 = G S1 S0 3:8 Decoder: O0 = G S2 S1 S0 O1 = G S2 S1 S0 O2 = G S2 S1 S0 O3 = G S2 S1 S0 O4 = G S2 S1 S0 O5 = G S2 S1 S0 O6 = G S2 S1 S0 O7 = G S2 S1 S

17 Gate level implementation of demultiplexers 1:2 decoders 2:4 decoders 33 Demultiplexers as general-purpose logic n:2 n decoder can implement any function of n variables with the variables used as control inputs the enable inputs tied to 1 and the appropriate minterms summed to form the function :8 DEC S2 S1 S0 'B'C' 'B'C 'BC' 'BC B'C' B'C BC' BC demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) B C 34 17

18 Demultiplexers as general-purpose logic (cont d) F1 = 'BC'D + 'B'CD + BCD F2 = BC'D' + BC F3 = (' + B' + C' + D') Enable 4:16 DEC 0 'B'C'D' 1 'B'C'D 2 'B'CD' 3 'B'CD 4 'BC'D' 5 'BC'D 6 'BCD' 7 'BCD 8 B'C'D' 9 B'C'D 10 B'CD' 11 B'CD 12 BC'D' 13 BC'D 14 BCD' 15 BCD B CD 35 Mux and demux combination Uses in multi-point connections 0 1 B0 B1 Sa MUX MUX Sb multiple input sources B Sum Ss DEMUX multiple output destinations S0 S

19 Summary What we ve covered so far: Number representations Switches and CMOS transistor gates Boolean algebra SOP and POS Logic minimization using K-maps Two and multi-level implementation Timing and Hazards OI, PL, PL, ROM implementation Mux and Demux What comes next: LU design Sequential circuits 37 19