FORDHAM UNIVERSITY CISC Dept. of Computer and Info. Science Spring, The Binary Adder

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1 FORDHAM UNIVERITY CIC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. cience pring, Introduction The Binar Adder The binar adder circuit is an important building block of digital arithmetic circuits. Its purpose is to form the sum of two binar numbers. In this article we will see how to design a binar adder out of basic gates. 2 Binar Addition The design of a binar adder begins b considering the process of addition in base 2, illustrated in Figure 1. In this example, the two numbers to be added, , are written one above the other. The carries from one position to the next (called internal carries) are written above them. The result is the 5-bit number Interpreting the values of the binar numbers, this sum corresponds to the decimal addition 13 6 = 19. From this example, we observe that the problem of adding two 4-bit numbers can be reduced to the problem of adding a column of two or three bits and passing the carr along to the next column. (For the sake of regularit, we can fill in a 0 as the input carr in the rightmost column, so then each column is alwas the sum of three bits.) 3 One-bit Full-Adder A circuit that adds a column of three bits is called a full-adder. (The name full-adder comes from the fact that it can be constructed b combining two half-adders, each of which adds onl two bits, in a wa that we shall see shortl.) We can design such a circuit b making a table listing the outputs for all possible input combinations. Note that in each column there is a sum bit which is put at the bottom and a carr bit that is taken to the next column. o we need to specif two output bits for each input combination. Let us call the two data bits x and. (These are the bits in the two Figure 1: ample 4-bit binar addition problem. The carries are shown above the two numbers being added. 1

2 z x C x z C Figure 2: mbolic addition of a column of three bits, and truth table specifing the results for each possible combination of inputs. bottom rows of the sum, corresponding to the given numbers to be added.) We call the input carr z. The output bits will be for the sum bit and C for the output carr. The summation is shown smbolicall in Figure 2, together with the table giving the outputs for each input combination. Each row of the table is filled in simpl b writing in binar the sum of the three bits x z, using 0 = 00, 1 = 01, 2 = 10, and 3 = um-of-minterms design From the truth-table, we can immediatel write the two functions C and as sums of minterms b following the rule that the included minterms are those that correspond to the rows where the function is 1: C = Σ(3, 5, 6, 7) = Σ(1, 2, 4, 7) Writing out the minterms as product terms, these sums correspond to C = xz xz xz xz = xz xz xz xz The corresponding circuit diagrams are shown in Figure More economical design The circuit shown in Figure 3 is not the simplest in terms of number of gates. If we measure cost b the number of gate inputs (which is roughl proportional to the number of transistors needed), the circuit has a cost of 32 gate inputs, but at least it is of depth 2, the minimum depth for an circuit except for rare special cases. One obvious economization is obtained b noting that C and share minterm 7, so it can be generated onl once and fanned out to both OR gates. This reduces the count of gate inputs b 3, to 29. A larger improvement can be obtained b noting that one can rewrite C as C = x z xz 2

3 C Figure 3: Full-adder implementation via sum of minterms form. x cs x c s Figure 4: mbolic addition of a column of two bits, and truth table specifing the results for each possible combination of inputs. The circuit implementing this expression has onl 9 gate inputs as compared to 16 for the C circuit in Figure 3, so the combined C and circuits would have onl 25 gate inputs. This turns out to be the most economical depth-2 implementation of the full-adder, since cannot be simplified beond the sum-of-minterms form. 3.3 Design based on half-adder A more economical circuit can be obtained if we allow the depth to be greater than 2. We begin this design b introducing the half-adder, which adds just two bits instead of 3. The truth-table for the half-adder is shown in Figure 4. A full-adder can be constructed from two half-adders and an OR gate, as shown in Figure 5. The explanation of wh this works is as follows. (In this paragraph, denotes addition, not the OR operation.) Consider the addition of xz. This can be grouped as (x ) z where (x ) represents the output of the half-adder that receives x and. This partial sum is added to z b the other half-adder, ielding the complete sum bit. As for C, consider that there are two possible was to make C = 1: first, if x = 2, then adding z can onl make the total sum 2 or 3, and either wa C = 1. In this case, the first half-adder s carr-out is a 1. econd, if x = 1, then C will be 1 onl if z = 1 to make the total sum 2. In this case, the second half-adder s carr output will be 1. Thus we see that C = 1 if and onl if at least one of the half-adders produces a carr-out of 1. This corresponds to the OR of the two partial carr bits. Now, to complete the design we need onl construct the half-adder out of basic gates. The straightforward design methodolog will not ield the simplest design. Instead we use some cleverness that will allow c and s to share some logic. 3

4 x z x c HA s x c HA s C Figure 5: Block diagram of full-adder implementation via a pair of half-adders. x z C Figure 6: Full-adder implementation via a pair of half-adders, expanded in terms of gates. The two half-adders are indicated b the dashed boxes. From the truth-table for the half-adder, we see c = Σ(3) = x s = Π(0, 3) = (x )(x ) Using DeMorgan s laws we can write the complement of s as s = (x ) (x ) = (x ) c Taking the complement of the last expression will ield s. Using this design for the half-adder, the circuit shown in Figure 5 can be implemented in terms of basic gates as shown in Figure 6. This circuit has 14 gate inputs, a large reduction from the previous design, but its depth is 4 (the longest path from input to output passes through 4 gates). The extra depth means it is slower than the depth-2 design. However, in the context of a multi-bit binar adder design using the fast carr technique, this extra depth turns out not to matter much because the carr propagation is the limiting factor for the overall depth of the adder, so this design is quite competitive. 4 Ripple Adder With the full-adder design in hand, we can now construct an n-bit adder simpl b stringing full-adders together. Each full-adder adds the bits in one bit position, sa i, where i = 0, 1,..., n 1. Thus the i-th full-adder receives the data bits A i and B i from the two numbers to be added. It also receives a carr-in C i from the full-adder in the 4

5 C 0 A 0 B 0 A 1 B 1 A 2 B 2 0 C 1 1 C 2 2 C 3 A 3 B 3 3 C 4 Figure 7: Four-bit binar adder implemented b connecting 4 full-adders together. next-lower-numbered bit position. It produces bit i of the sum, and sends a carr-out C i1 to the full-adder in the next-higher-numbered bit position. The full-adder for the least-significant bit, i = 0, is an exception: it receives its carr-in from an external source. The full-adder for the most-significant bit, i = n 1, is also an exception: its carr-out is sent out externall as the end-carr C n. Figure 7 shows such a design for n = 4. This design is called a ripple-adder because the internal carries ripple down the chain from one full-adder to the next. It is an economical design in terms of the number of gate inputs needed, but suffers the disadvantage that the depth increases linearl with the number of bits in the operands. To sum operands of 16 or more bits, such a design would be too slow to be competitive. The speed of the adder can be increased b using a fast-carr technique. uch techniques increase the speed with which the internal carries are generated, but at the expense of increasing the number of gate inputs needed to implement the circuit. Fast-carr techniques are not discussed here, since the are covered b Patterson and Henness in ection C.6. Here we will onl note that the circuit of Figure 6 produces the carr generate and propagate functions discussed there from the half-adder that receives x and. The generate function is x which is the output of the upper AND gate, and the propagate function is x which is the complement of the output of the lower AND gate. o that circuit is well suited to be used in a design based on a fast-carr technique. 5 Exercises The correctness of the full-adder design based on half-adders was justified informall in section 3.3. Give a formal proof that the circuit in Figure 6 is a full-adder, 1. b constructing a truth table showing the intermediate signals and the outputs, propagating the logic relationships specified b the circuit diagram. 2. b obtaining the boolean expressions for C and that correspond to the circuit diagram, and simplifing them using the various laws of boolean algebra until the are recognizabl the same as one of the other expressions obtained earlier (e.g. sum-of-minterms form). 5