03 Logic networks Gate-level design. Design metrics
|
|
- Judith Nash
- 8 years ago
- Views:
Transcription
1 03 Logic networks Design metrics Design styles Examples Adders alessandro bogliolo isti information science and technology institute /8 Design metrics Area (A) Number of gates Number of -input NANDs Number of gates inputs Performance Propagation time (delay): pin-to-pin, overall (Tp) Contamination time: pin-to-pin, overall (Tc) Throughput (rate) Power Static (W) Dynamic (W) alessandro bogliolo isti information science and technology institute /8
2 Prop. and Cont. Time (ex) in out Tp A Out Out Tc A Out Out B B alessandro bogliolo isti information science and technology institute 3/8 Prop. and Cont. Time (ex) alessandro bogliolo isti information science and technology institute 4/8
3 Prop. and Cont. Time (ex3) alessandro bogliolo isti information science and technology institute 5/8 Prop. and Cont. Time (ex4) alessandro bogliolo isti information science and technology institute 6/8 3
4 Design approaches Logic synthesis: General Inefficient Non-scalable Example: Boolean functions of a few variables Top-down problem partitioning: Application-specific Modular Scalable Example: Arithmetic operators alessandro bogliolo isti information science and technology institute 7/8 T-D Example: Ripple-carry adder Functional specification: S=A+B alessandro bogliolo isti information science and technology institute 8/8 4
5 T-D Example: Full adder () Functional specification: Cin A B S Cout S = Cin' A' B + Cin' AB' + CinA' B' + CinAB S = Cin' ( A' B + AB') + Cin( A' B' + AB) S = Cin'( A B) + Cin( A B)' = Cin A B alessandro bogliolo isti information science and technology institute 9/8 T-D Example: Full adder () Functional specification: Cin A B S Cout Cout = Cin' AB + CinA' B + CinAB' + CinAB Cout = Cin' AB + Cin( A + B) Cout = Cin' AB + Cin( A + B + AB) Cout = AB + Cin( A + B) alessandro bogliolo isti information science and technology institute 0/8 5
6 T-D Example: Full adder (3) Putting it all together: S = Cin ( A B) Cout = AB + Cin( A + B) Cout = AB + Cin( A B + AB) Cout = AB + Cin( A B) Cout = (( AB)' + ( Cin( A B))')' alessandro bogliolo isti information science and technology institute /8 Adders. Ripple-Carry Adder (RCA). Synchronous RCA 3. Pipelined RCA 4. Bit-serial Adder 5. Carry-Lookahead Adder alessandro bogliolo isti information science and technology institute /8 6
7 Ripple-carry adder (RCAn) A(RCAn) = n A(FA) = O(n) Tp(RCAn) = n Tp(FA) = O(n) Tc(RCAn) = Tc(FA) = O() Rate(RCAn) < /Tp(RCAn) = O(/n) alessandro bogliolo isti information science and technology institute 3/8 Synchronous RCAn (SRCAn) A(SincRCAn) = na(fa) + n(n-)a(ff) = O(n ) Tp(SincRCAn) = ntclk > ntp(fa) = O(n) Tc(SincRCAn) = ntclk > ntp(fa) = O(n) Rate(SincRCAn) = /(ntclk) = O(/n) alessandro bogliolo isti information science and technology institute 4/8 7
8 Pipelined RCAn (PRCAn) A(PRCAn) = na(fa) + n(n-)a(ff) = O(n ) Tp(PRCAn) = ntclk > ntp(fa) = O(n) Tc(PRCAn) = ntclk > ntp(fa) = O(n) Rate(PRCAn) = /Tclk = O() alessandro bogliolo isti information science and technology institute 5/8 Bit-serial adder (BSAn) A(BSAn) = A(FA) + A(FF) = O() Tp(BSAn) = ntclk > ntp(fa) = O(n) Tc(BSAn) = Tclk > Tp(FA) = O() Rate(BSAn) = /(ntclk) = O(/n) alessandro bogliolo isti information science and technology institute 6/8 8
9 Carry Lookahead Adder (CLAn) Observations: c i = a i *b i + (a i +b i )c i- = g i + p i * c i- The first term generates the carry out (generate g i = a i *b i ) The second term propagates the carry (propagate p i = a i +b i ) Implementation: c i = g i + p i (g i- +p i- (g i- +p i- (... (g 0 +p 0 *Cin)...))) c i = g i + p i g i- +p i p i- g i- + p i p i- p i- g i p i p i- p i-...p 0 Cin () () (3) alessandro bogliolo isti information science and technology institute 7/8 Carry Lookahead Adder (CLAn) Unit delay model A(CLAn) = A(FA 0 )+ +A(FA n- ) = A(FA 0 )+ +O(n ) = O(n 3 ) Tp(CLAn) = Tp(FA) = O() Tc(CLAn) = Tc(FA 0 ) = O() Rate(CLAn) > /Tp(CLAn) = O() Gate delay proportional to the number of inputs A(CLAn) = A(FA 0 )+ +A(FA n- ) = A(FA 0 )+ +O(n ) = O(n 3 ) Tp(CLAn) = Tp(FA n- ) = O(n) Tc(CLAn) = Tc(FA 0 ) = O() Rate(CLAn) > /Tp(CLAn) = O(/n) Actual O(n) < A(CLAn) < O(n 3 ) O() < Tp(CLAn) < O(n) Tc(CLAn) = O() O(/n) < Rate(CLAn) < O() alessandro bogliolo isti information science and technology institute 8/8 9
exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576
exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576 Outline exclusive OR gate (XOR) Definition Properties Examples of Applications Odd Function Parity Generation and Checking
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationNAME AND SURNAME. TIME: 1 hour 30 minutes 1/6
E.T.S.E.T.B. MSc in ICT FINAL EXAM VLSI Digital Design Spring Course 2005-2006 June 6, 2006 Score publication date: June 19, 2006 Exam review request deadline: June 22, 2006 Academic consultancy: June
More informationCSE140 Homework #7 - Solution
CSE140 Spring2013 CSE140 Homework #7 - Solution You must SHOW ALL STEPS for obtaining the solution. Reporting the correct answer, without showing the work performed at each step will result in getting
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More informationLecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay
More informationCSE140: Components and Design Techniques for Digital Systems
CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing What we covered thus far: Number representations Logic gates Boolean algebra Introduction to CMOS HW#2 due, HW#3 assigned
More informationMore Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.
More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input [7:0] D; output [7:0] Q; reg [7:0] Q; if (reset) Q = 0; else Q = D; module // reg8 Verilog - 1 Verilog
More informationBinary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders
SE 370 Spring 2006 Introduction to Digital Design Lecture 12: dders Last Lecture Ls and Ls Today dders inary full 1-bit full omputes sum, carry-out arry-in allows cascaded s = xor xor = + + 32 ND2 11 ND2
More informationSystem on Chip Design. Michael Nydegger
Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What
More informationAdder.PPT(10/1/2009) 5.1. Lecture 13. Adder Circuits
Adder.T(//29) 5. Lecture 3 Adder ircuits Objectives Understand how to add both signed and unsigned numbers Appreciate how the delay of an adder circuit depends on the data values that are being added together
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
More information5 Combinatorial Components. 5.0 Full adder. Full subtractor
5 Combatorial Components Use for data transformation, manipulation, terconnection, and for control: arithmetic operations - addition, subtraction, multiplication and division. logic operations - AND, OR,
More informationXilinx ISE. <Release Version: 10.1i> Tutorial. Department of Electrical and Computer Engineering State University of New York New Paltz
Xilinx ISE Tutorial Department of Electrical and Computer Engineering State University of New York New Paltz Fall 2010 Baback Izadi Starting the ISE Software Start ISE from the
More informationLatches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More informationLecture 11: Sequential Circuit Design
Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing
More informationList of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).
G. H. RAISONI COLLEGE OF ENGINEERING, NAGPUR Department of Electronics & Communication Engineering Branch:-4 th Semester[Electronics] Subject: - Digital Circuits List of Experiment Sr. Name Of Experiment
More information路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationVHDL GUIDELINES FOR SYNTHESIS
VHDL GUIDELINES FOR SYNTHESIS Claudio Talarico For internal use only 1/19 BASICS VHDL VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware description language that allows
More informationHigh Speed Gate Level Synchronous Full Adder Designs
High Speed Gate Level Synchronous Full Adder Designs PADMANABHAN BALASUBRAMANIAN and NIKOS E. MASTORAKIS School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UNITED
More information01 Introduction. The timeline
01 Introduction The pre-mechanical era The mechanical era The electromechanical era The electronic era The microelectronic era The roadmap for the next 10 years alessandro bogliolo isti information science
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)
ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment
More informationNetworked Embedded Systems: Design Challenges
Networked Embedded Systems: Design Challenges Davide Quaglia Electronic Systems Design Group University of Verona 3 a giornata nazionale di Sintesi Logica, Verona, Jun 21, 2007 Outline Motivation Networked
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationUnited States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1
United States Naval Academy Electrical and Computer Engineering Department EC262 Exam 29 September 2. Do a page check now. You should have pages (cover & questions). 2. Read all problems in their entirety.
More informationGate Delay Model. Estimating Delays. Effort Delay. Gate Delay. Computing Logical Effort. Logical Effort
Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter 1 is on our web page Also Chapter 4 in our textbook
More informationModule 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits Objectives In this lecture you will learn the following Introduction Logical Effort of an Inverter
More informationSequential Circuit Design
Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
More informationCONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is CONTENTS PREFACE xv 1 INTRODUCTION 1 1.1 About Digital Design 1 1.2 Analog versus Digital 3 1.3 Digital Devices
More informationModule-I Lecture-I Introduction to Digital VLSI Design Flow
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-I Lecture-I Introduction to Digital VLSI Design Flow Introduction The functionality of electronics equipments and gadgets
More informationEE360: Digital Design I Course Syllabus
: Course Syllabus Dr. Mohammad H. Awedh Fall 2008 Course Description This course introduces students to the basic concepts of digital systems, including analysis and design. Both combinational and sequential
More informationUnderstanding Logic Design
Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1
More informationENGI 241 Experiment 5 Basic Logic Gates
ENGI 24 Experiment 5 Basic Logic Gates OBJECTIVE This experiment will examine the operation of the AND, NAND, OR, and NOR logic gates and compare the expected outputs to the truth tables for these devices.
More informationECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
More informationSequential Circuits. Combinational Circuits Outputs depend on the current inputs
Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating
More informationBinary Adders: Half Adders and Full Adders
Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order
More informationMULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output
More informationearlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder.
The circuit created is an 8-bit adder. The 8-bit adder adds two 8-bit binary inputs and the result is produced in the output. In order to create a Full 8-bit adder, I could use eight Full -bit adders and
More informationCOMPUTER SCIENCE 1999 (Delhi Board)
COMPUTER SCIENCE 1999 (Delhi Board) Time allowed: 3 hours Max. Marks: 70 Instructions: (i) All the questions are compulsory. (ii) Programming Language: C++ QUESTION l. (a) Why main function is special?
More informationBoolean Expressions, Conditions, Loops, and Enumerations. Precedence Rules (from highest to lowest priority)
Boolean Expressions, Conditions, Loops, and Enumerations Relational Operators == // true if two values are equivalent!= // true if two values are not equivalent < // true if left value is less than the
More informationFPGA. AT6000 FPGAs. Application Note AT6000 FPGAs. 3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs.
3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 s Introduction Convolution is one of the basic and most common operations in both analog and digital domain signal processing.
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
More informationHIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER
HIGH SPEED AREA EFFICIENT 1-BIT HYBRID FULL ADDER Sachin Kumar *1, Aman Kumar #2, Puneet Bansal #3 * Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, India # University Institute
More informationHardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner
Hardware Implementations of RSA Using Fast Montgomery Multiplications ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Overview Introduction Functional Specifications Implemented Design and Optimizations
More informationCombinational Logic Design
Chapter 4 Combinational Logic Design The foundations for the design of digital logic circuits were established in the preceding chapters. The elements of Boolean algebra (two-element switching algebra
More informationDigital Design. A Systems Approach
Digital Design A Systems Approach This introductory textbook provides students with a system-level perspective and the tools they need to understand, analyze, and design digital systems. It goes beyond
More informationDigital Circuit Design
Test and Diagnosis of of ICs Fault coverage (%) 95 9 85 8 75 7 65 97.92 SSL 4,246 Shawn Blanton Professor Department of ECE Center for Silicon System Implementation CMU Laboratory for Integrated Systems
More informationPIC 10A. Lecture 7: Graphics II and intro to the if statement
PIC 10A Lecture 7: Graphics II and intro to the if statement Setting up a coordinate system By default the viewing window has a coordinate system already set up for you 10-10 10-10 The origin is in the
More informationTIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING
TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453
More informationWhat is a Loop? Pretest Loops in C++ Types of Loop Testing. Count-controlled loops. Loops can be...
What is a Loop? CSC Intermediate Programming Looping A loop is a repetition control structure It causes a single statement or a group of statements to be executed repeatedly It uses a condition to control
More informationInternational Journal of Electronics and Computer Science Engineering 1482
International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant
More informationSignal integrity in deep-sub-micron integrated circuits
Signal integrity in deep-sub-micron integrated circuits Alessandro Bogliolo abogliolo@ing.unife.it Outline Introduction General signaling scheme Noise sources and effects in DSM ICs Supply noise Synchronization
More informationHECTOR a software model checker with cooperating analysis plugins. Nathaniel Charlton and Michael Huth Imperial College London
HECTOR a software model checker with cooperating analysis plugins Nathaniel Charlton and Michael Huth Imperial College London Introduction HECTOR targets imperative heap-manipulating programs uses abstraction
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationA New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
A New Reversible TSG Gate and Its Application For Designing Efficient Adder s Himanshu Thapliyal Center for VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad-500019,
More informationThree-Phase Dual-Rail Pre-Charge Logic
Infineon Page 1 CHES 2006 - Yokohama Three-Phase Dual-Rail Pre-Charge Logic L. Giancane, R. Luzzi, A. Trifiletti {marco.bucci, raimondo.luzzi}@infineon.com {giancane, trifiletti}@die.mail.uniroma1.it Summary
More informationHunting Asynchronous CDC Violations in the Wild
Hunting Asynchronous Violations in the Wild Chris Kwok Principal Engineer May 4, 2015 is the #2 Verification Problem Why is a Big Problem: 10 or More Clock Domains are Common Even FPGA Users Are Suffering
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on
More informationInnovative improvement of fundamental metrics including power dissipation and efficiency of the ALU system
Innovative improvement of fundamental metrics including power dissipation and efficiency of the ALU system Joseph LaBauve Department of Electrical and Computer Engineering University of Central Florida
More informationA Link Load Balancing Solution for Multi-Homed Networks
A Link Load Balancing Solution for Multi-Homed Networks Overview An increasing number of enterprises are using the Internet for delivering mission-critical content and applications. By maintaining only
More informationKing Fahd University of Petroleum & Minerals Computer Engineering g Dept
King Fahd University of Petroleum & Minerals Computer Engineering g Dept COE 543 Mobile and Wireless Networks Term 111 Dr. Ashraf S. Hasan Mahmoud Rm 22-148-3 Ext. 1724 Email: ashraf@kfupm.edu.sa 12/24/2011
More informationDesign of Low Power One-Bit Hybrid-CMOS Full Adder Cells
Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Sushil B. Bhaisare 1, Sonalee P. Suryawanshi 2, Sagar P. Soitkar 3 1 Lecturer in Electronics Department, Nagpur University, G.H.R.I.E.T.W. Nagpur,
More informationParallel Scalable Algorithms- Performance Parameters
www.bsc.es Parallel Scalable Algorithms- Performance Parameters Vassil Alexandrov, ICREA - Barcelona Supercomputing Center, Spain Overview Sources of Overhead in Parallel Programs Performance Metrics for
More informationFault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults. Transistor faults Summary
Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at
More informationAn Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths N. KRANITIS M. PSARAKIS D. GIZOPOULOS 2 A. PASCHALIS 3 Y. ZORIAN 4 Institute of Informatics & Telecommunications, NCSR
More informationAcademic year: 2015/2016 Code: IES-1-307-s ECTS credits: 6. Field of study: Electronics and Telecommunications Specialty: -
Module name: Digital Electronics and Programmable Devices Academic year: 2015/2016 Code: IES-1-307-s ECTS credits: 6 Faculty of: Computer Science, Electronics and Telecommunications Field of study: Electronics
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationSistemas Digitais I LESI - 2º ano
Sistemas Digitais I LESI - 2º ano Lesson 6 - Combinational Design Practices Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA - PLDs (1) - The
More informationPipelining Review and Its Limitations
Pipelining Review and Its Limitations Yuri Baida yuri.baida@gmail.com yuriy.v.baida@intel.com October 16, 2010 Moscow Institute of Physics and Technology Agenda Review Instruction set architecture Basic
More informationProject Management Life Cycle (PMLC)
Project Management Life Cycle (PMLC) Page 2 Project Management Life Cycle (PMLC) Introduction PMLC Working Group IT Business Process Management(BPM) IT Project Management Office (PMO) Finance System Support
More informationHigh-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
More informationOptimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks Cheoljoo Jeong Steven M. Nowick Department of Computer Science Columbia University Outline Introduction Background Technology
More informationList of courses MEngg (Computer Systems)
List of courses MEngg (Computer Systems) Course No. Course Title Non-Credit Courses CS-401 CS-402 CS-403 CS-404 CS-405 CS-406 Introduction to Programming Systems Design System Design using Microprocessors
More informationRead-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards
Points ddressed in this Lecture Lecture 8: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic
More informationFlip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationProgrammable Logic Controllers Definition. Programmable Logic Controllers History
Definition A digitally operated electronic apparatus which uses a programmable memory for the internal storage of instructions for implementing specific functions such as logic, sequencing, timing, counting,
More informationImplementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2)
Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3, Number 6 (2013), pp. 683-690 Research India Publications http://www.ripublication.com/aeee.htm Implementation of Modified Booth
More informationExample-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm Computer Technology /99 Overview Ultra-Low-Power
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationRUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY
RUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY Fall 2012 Contents 1 LABORATORY No 1 3 11 Equipment 3 12 Protoboard 4 13 The Input-Control/Output-Display
More informationThe concept of hierarchical design: the views of computer science and engineering students
The concept of hierarchical design: the views of computer science and engineering students Lambrini Adamopoulou, Maria Kordaki and George Alexiou Department of Computer Engineering and Informatics, Patras
More informationGetting the Most Out of Synthesis
Outline Getting the Most Out of Synthesis Dr. Paul D. Franzon 1. Timing Optimization Approaches 2. Area Optimization Approaches 3. Design Partitioning References 1. Smith and Franzon, Chapter 11 2. D.Smith,
More informationComputer Networks CS321
Computer Networks CS321 Dr. Ramana I.I.T Jodhpur Dr. Ramana ( I.I.T Jodhpur ) Computer Networks CS321 1 / 22 Outline of the Lectures 1 Introduction OSI Reference Model Internet Protocol Performance Metrics
More informationSequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationBuilding Blocks for Digital Design
Building Blocks for Digital Design The construction of most digital systems is a large task. Disciplined designers in any field will subdivide the original task into manageable subunits building blocks
More informationQualitative modeling of biological systems
Qualitative modeling of biological systems The functional form of regulatory relationships and kinetic parameters are often unknown Increasing evidence for robustness to changes in kinetic parameters.
More informationLFSR BASED COUNTERS AVINASH AJANE, B.E. A technical report submitted to the Graduate School. in partial fulfillment of the requirements
LFSR BASED COUNTERS BY AVINASH AJANE, B.E A technical report submitted to the Graduate School in partial fulfillment of the requirements for the degree Master of Science in Electrical Engineering New Mexico
More informationchapater 7 : Distributed Database Management Systems
chapater 7 : Distributed Database Management Systems Distributed Database Management System When an organization is geographically dispersed, it may choose to store its databases on a central database
More informationClassification - Examples
Lecture 2 Scheduling 1 Classification - Examples 1 r j C max given: n jobs with processing times p 1,...,p n and release dates r 1,...,r n jobs have to be scheduled without preemption on one machine taking
More informationDelay Characterization in FPGA-based Reconfigurable Systems
Institute of Computer Architecture and Computer Engineering University of Stuttgart Pfaffenwaldring 47 D 70569 Stuttgart Master s Thesis Nr. 3505 Delay Characterization in FPGA-based Reconfigurable Systems
More informationA single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc
Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into acc
More informationSCALABILITY AND AVAILABILITY
SCALABILITY AND AVAILABILITY Real Systems must be Scalable fast enough to handle the expected load and grow easily when the load grows Available available enough of the time Scalable Scale-up increase
More informationArchitectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
More information