Elementary Logic Gates

Transcription

1 Elementary Logic Gates Name Symbol Inverter (NOT Gate) ND Gate OR Gate Truth Table Logic Equation = = = = = + C. E. Stroud Combinational Logic Design (/6)

2 Other Elementary Logic Gates NND Gate NOR Gate (NOT ND) (NOT OR) Name Symbol = ( ) = Truth Table Logic Equation = ( + ) = + C. E. Stroud Combinational Logic Design (/6) 2

3 Using Truth Tables to Prove Theorems DeMorgan s Theorems T8a: (+) = T8b: ( ) = + a NOR gate is equivalent to an ND gate with inverted inputs NOR NOR a NND gate is equivalent to an OR gate with inverted inputs NND alternate logic symbols C. E. Stroud Combinational Logic Design (/6) 3 NND

4 Other Logic Gates Name Symbol uffer Exclusive-OR Gate aka OR Gate Exclusive-NOR Gate aka NOR or NOR Gate Truth Table Logic Equation = = = + = = + also denoted = C. E. Stroud Combinational Logic Design (/6) 4

5 Interesting Properties of Exclusive-OR Controlled inverter = = OR with one input inverted = NOR = =( ) NOR with one input inverted = OR ( ) =( ) = Constant output = = C. E. Stroud Combinational Logic Design (/6) 5

6 Exclusive-OR Implementations = + OR & NOR not considered elementary logic gates by many designers 4 gates () (() ) (() ) =((() ) (() ) ) = = + = (+) + (+) = = + C. E. Stroud Combinational Logic Design (/6) 6 5 gates 3 gates (+) =((+) +) = ++ = (+) = (+)(+) = = = +

7 Functionally Complete Set of Gates If any digital circuit can be built from a set of gates, that set is said to be functionally complete Functionally complete sets of gates: ND, OR, & NOT NND NOR Multiplexers To show a set of gates is functionally complete, we must show that you can construct ND, OR and NOT functions C. E. Stroud Combinational Logic Design (/6) 7

8 Functionally Complete Set of Gates = = The NND gate is functionally complete We can build any digital logic circuit out of all NND gates Same holds true for the NOR gate and the multiplexer The OR & NOR are not functionally complete =+ using DeMorgan s Theorem C. E. Stroud Combinational Logic Design (/6) 8

9 Gate-level Representations SOP expressions ND-OR With inverters for complemented literals = C+ C+C +C aka 2-level ND-OR logic representation POS expressions OR-ND With inverters for complemented literals =(++C) (+ +C) ( ++C) ( ++C ) aka 2-level OR-ND logic representation C C 8 gates C. E. Stroud Combinational Logic Design (/6) 9

10 Gate Level Representation from oolean equation = ((( ) C) +D ) = (( ) C)+D ( ) C D (( ) C) D C. E. Stroud Combinational Logic Design (/6)

11 Circuit nalysis Going from gate-level to truth table pply s & s to inputs to get outputs oolean equation Move equations to output =(+ )C+ C =C+ C+ C C C + (+ )C C C C. E. Stroud Combinational Logic Design (/6)

12 Circuit nalysis We can implement different circuits for same logic function that are functionally equivalent (produce the correct output response for all input values) Which implementation is the best? Depends on design goals and criteria rea analysis Number of gates, G (most commonly used) Number of gate inputs and outputs, G IO (more accurate) igger gates take up more area Performance analysis (worst case path from inputs to outputs) Number of gates in worst case path from input to output, G del More accurate delay measurement per gate Propagation delay = intrinsic (internal) delay + extrinsic (external) delay Relative prop delay, P del = # inputs to gate (intrinsic) + # loads (extrinsic) C. E. Stroud Combinational Logic Design (/6) 2

13 Circuit nalysis Example From previous example: =(+ )C+ C # gates: G = 7 # gate I/O: G IO = 9 Gate delay: G del = 4 worst case path: Prop delay: P del = 2 worst case path: 2 2 C C (+ )C C 3+ C. E. Stroud Combinational Logic Design (/6) 3

14 Circuit Optimization Obviously we want smallest, fastest circuit Some asic Goals: Minimizing # product terms minimizes # of ND gates and # inputs to OR gate in a 2-level SOP (ND-OR) representation Minimizing # literals in each product term minimizes # inputs to its ND gate We can use postulates & theorems, but It would be nice to find a more reliable procedure C. E. Stroud Combinational Logic Design (/6) 4