CONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii

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1 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is CONTENTS PREFACE xv 1 INTRODUCTION About Digital Design Analog versus Digital Digital Devices Electronic Aspects of Digital Design Software Aspects of Digital Design Integrated Circuits Programmable Logic Devices Application-Specific ICs Printed-Circuit Boards Digital-Design Levels The Name of the Game Going Forward 23 Drill Problems 23 2 NUMBER SYSTEMS AND CODES Positional Number Systems Octal and Hexadecimal Numbers General Positional-Number-System Conversions Addition and Subtraction of Nondecimal Numbers Representation of Negative Numbers Signed-Magnitude Representation Complement Number Systems Radix-Complement Representation Two s-complement Representation Diminished Radix-Complement Representation Ones -Complement Representation Excess Representations 2.6 Two s-complement Addition and Subtraction Addition Rules A Graphical View Overflow Subtraction Rules Two s-complement and Unsigned Binary Numbers 2.7 Ones -Complement Addition and Subtraction Binary Multiplication 45 vii

2 viii 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is 2.9 Binary Division Binary Codes for Decimal Numbers Gray Code Character Codes Codes for Actions, Conditions, and States n-cubes and Distance Codes for Detecting and Correcting Errors Error-Detecting Codes Error-Correcting and Multiple-Error-Detecting Codes Hamming Codes CRC Codes Two-Dimensional Codes Checksum Codes m-out-of-n Codes 2.16 Codes for Serial Data Transmission and Storage Parallel and Serial Data Serial Line Codes References 73 Drill Problems 74 Exercises 76 3 DIGITAL CIRCUITS Logic Signals and Gates Logic Families CMOS Logic CMOS Logic Levels MOS Transistors Basic CMOS Inverter Circuit CMOS NAND and NOR Gates Fan-In Noninverting Gates CMOS AND-OR-INVERT and OR-AND-INVERT Gates 3.4 Electrical Behavior of CMOS Circuits Overview Data Sheets and Specifications 3.5 CMOS Static Electrical Behavior Logic Levels and Noise Margins Circuit Behavior with Resistive Loads Circuit Behavior with Nonideal Inputs Fanout Effects of Loading Unused Inputs How to Destroy a CMOS Device 3.6 CMOS Dynamic Electrical Behavior Transition Time Propagation Delay Power Consumption Current Spikes and Decoupling Capacitors Inductive Effects Simultaneous Switching and Ground Bounce 3.7 Other CMOS Input and Output Structures Transmission Gates Schmitt-Trigger Inputs Three-State Outputs Open-Drain Outputs Driving LEDs Multisource Buses Wired Logic Pull-Up Resistors

3 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is 3.8 CMOS Logic Families HC and HCT AHC and AHCT HC, HCT, AHC, and AHCT Electrical Characteristics AC and ACT FCT and FCT-T FCT-T Electrical Characteristics 3.9 Low-Voltage CMOS Logic and Interfacing V LVTTL and LVCMOS Logic V Tolerant Inputs V Tolerant Outputs TTL/LVTTL Interfacing Summary Logic Levels Less Than 3.3 V 3.10 Bipolar Logic Diode Logic Bipolar Junction Transistors Transistor-Transistor Logic TTL Logic Levels and Noise Margins TTL Fanout TTL Families A TTL Data Sheet CMOS/TTL Interfacing Emitter-Coupled Logic References 174 Drill Problems 175 Exercises COMBINATIONAL LOGIC DESIGN PRINCIPLES Switching Algebra Axioms Single-Variable Theorems Two- and Three-Variable Theorems n-variable Theorems Duality Standard Representations of Logic Functions 4.2 Combinational-Circuit Analysis Combinational-Circuit Synthesis Circuit Descriptions and Designs Circuit Manipulations Combinational-Circuit Minimization Karnaugh Maps Minimizing Sums of Products Other Minimization Topics Programmed Minimization Methods 4.4 Timing Hazards Static Hazards Finding Static Hazards Using Maps Dynamic Hazards Designing Hazard-Free Circuits References 229 Drill Problems 230 Exercises HARDWARE DESCRIPTION LANGUAGES HDL-Based Digital Design Why HDLs? HDL Tool Suites HDL-Based Design Flow 5.2 The ABEL Hardware Description Language ABEL Program Structure ABEL Compiler Operation WHEN Statements and Equation Blocks Truth Tables Ranges, Sets, and Relations Test Vectors Additional ABEL Features ix

4 x 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is 5.3 The VHDL Hardware Description Language Program Structure Types, Constants, and Arrays Functions and Procedures Libraries and Packages Structural Design Elements Dataflow Design Elements Behavioral Design Elements The Time Dimension Simulation Test Benches VHDL Features for Sequential Logic Design Synthesis 5.4 The Verilog Hardware Description Language Program Structure Logic System, Nets, Variables, and Constants Vectors and Operators Arrays Logical Operators and Expressions Compiler Directives Structural Design Elements Dataflow Design Elements Behavioral Design Elements (Procedural Code) Functions and Tasks The Time Dimension Simulation Test Benches Verilog Features for Sequential Logic Design Synthesis References 335 Drill Problems 337 Exercises COMBINATIONAL LOGIC DESIGN PRACTICES Documentation Standards Block Diagrams Gate Symbols Signal Names and Active Levels Active Levels for Pins Bubble-to-Bubble Logic Design Signal Naming in HDL Programs Drawing Layout Buses Additional Schematic Information 6.2 Circuit Timing Timing Diagrams Propagation Delay Timing Specifications Timing Analysis Timing Analysis Tools 6.3 Combinational PLDs Programmable Logic Arrays Programmable Array Logic Devices Generic Array Logic Devices Complex Programmable Logic Devices (CPLDs) CMOS PLD Circuits Device Programming and Testing 6.4 Decoders Binary Decoders Logic Symbols for Larger-Scale Elements The 74x138 3-to-8 Decoder Cascading Binary Decoders Decoders in ABEL and PLDs Decoders in VHDL Decoders in Verilog Seven-Segment Decoders 6.5 Encoders Priority Encoders The 74x148 Priority Encoder Encoders in ABEL and PLDs Encoders in VHDL Encoders in Verilog

5 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is 6.6 Three-State Devices Three-State Buffers Standard MSI Three-State Buffers Three-State Outputs in ABEL and PLDs Three-State Outputs in VHDL Three-State Outputs in Verilog 6.7 Multiplexers Standard MSI Multiplexers Expanding Multiplexers Multiplexers, Demultiplexers, and Buses Multiplexers in ABEL and PLDs Multiplexers in VHDL Multiplexers in Verilog 6.8 Exclusive-OR Gates and Parity Circuits Exclusive-OR and Exclusive-NOR Gates Parity Circuits The 74x280 9-Bit Parity Generator Parity-Checking Applications Exclusive-OR Gates and Parity Circuits in ABEL and PLDs Exclusive-OR Gates and Parity Circuits in VHDL Exclusive-OR Gates and Parity Circuits in Verilog 6.9 Comparators Comparator Structure Iterative Circuits An Iterative Comparator Circuit Standard MSI Magnitude Comparators Comparators in HDLs Comparators in ABEL and PLDs Comparators in VHDL Comparators in Verilog 6.10 Adders, Subtractors, and ALUs Half Adders and Full Adders Ripple Adders Subtractors Carry-Lookahead Adders MSI Adders MSI Arithmetic and Logic Units Group-Carry Lookahead Adders in ABEL and PLDs Adders in VHDL Adders in Verilog 6.11 Combinational Multipliers Combinational Multiplier Structures Multiplication in ABEL and PLDs Multiplication in VHDL Multiplication in Verilog References 508 Drill Problems 509 Exercises SEQUENTIAL LOGIC DESIGN PRINCIPLES Bistable Elements Digital Analysis Analog Analysis Metastable Behavior 7.2 Latches and Flip-Flops S-R Latch S-R Latch S-R Latch with Enable D Latch Edge-Triggered D Flip-Flop Edge-Triggered D Flip-Flop with Enable Scan Flip-Flop Master/Slave S-R Flip-Flop Master/Slave J-K Flip-Flop Edge-Triggered J-K Flip-Flop T Flip-Flop xi

6 xii 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is 7.3 Clocked Synchronous State-Machine Analysis State-Machine Structure Output Logic Characteristic Equations Analysis of State Machines with D Flip-Flops 7.4 Clocked Synchronous State-Machine Design State-Table Design Example State Minimization State Assignment Synthesis Using D Flip-Flops Synthesis Using J-K Flip-Flops More Design Examples Using D Flip-Flops 7.5 Designing State Machines Using State Diagrams State-Machine Synthesis Using Transition Lists Transition Equations Excitation Equations Variations on the Scheme Realizing the State Machine 7.7 Another State-Machine Design Example The Guessing Game Unused States Output-Coded State Assignment Don t-care State Codings 7.8 Decomposing State Machines Feedback Sequential-Circuit Analysis Basic Analysis Analyzing Circuits with Multiple Feedback Loops Races State Tables and Flow Tables CMOS D Flip-Flop Analysis 7.10 Feedback Sequential-Circuit Design Latches Designing Fundamental-Mode Flow Table Flow-Table Minimization Race-Free State Assignment Excitation Equations Essential Hazards Summary 7.11 ABEL Sequential-Circuit Design Features Registered Outputs State Diagrams External State Memory Specifying Moore Outputs Specifying Mealy and Pipelined Outputs with WITH Test Vectors 7.12 Sequential-Circuit Design with VHDL Clocked Circuits State-Machine Design with VHDL A VHDL State-Machine Example State Assignment in VHDL Pipelined Outputs in VHDL Direct VHDL Coding Without a State Table More VHDL State-Machine Examples Specifying Flip-Flops in VHDL VHDL State-Machine Test Benches Feedback Sequential Circuits 7.13 Sequential-Circuit Design with Verilog Clocked Circuits State-Machine Design with Verilog A Verilog State-Machine Example Pipelined Outputs in Verilog Direct Verilog Coding Without a State Table More Verilog State-Machine Examples

7 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is Specifying Flip-Flops in Verilog Verilog State-Machine Test Benches Feedback Sequential Circuits References 663 Drill Problems 664 Exercises SEQUENTIAL LOGIC DESIGN PRACTICES Sequential-Circuit Documentation Standards General Requirements Logic Symbols State-Machine Descriptions Timing Diagrams and Specifications 8.2 Latches and Flip-Flops SSI Latches and Flip-Flops Switch Debouncing The Simplest Switch Debouncer Bus Holder Circuit Multibit Registers and Latches Registers and Latches in ABEL and PLDs Registers and Latches in VHDL Registers and Latches in Verilog 8.3 Sequential PLDs Sequential GAL Devices PLD Timing Specifications 8.4 Counters Ripple Counters Synchronous Counters MSI Counters and Applications Decoding Binary-Counter States Counters in ABEL and PLDs Counters in VHDL Counters in Verilog 8.5 Shift Registers Shift-Register Structure MSI Shift Registers Shift-Register Counters Ring Counters Johnson Counters Linear Feedback Shift-Register Counters Shift Registers in ABEL and PLDs Shift Registers in VHDL Shift Registers in Verilog Iterative versus Sequential Circuits Synchronous Design Methodology Synchronous System Structure 8.8 Impediments to Synchronous Design Clock Skew Gating the Clock Asynchronous Inputs 8.9 Synchronizer Failure and Metastability Synchronizer Failure Metastability Resolution Time Reliable Synchronizer Design Analysis of Metastable Timing Better Synchronizers Other Synchronizer Designs Synchronizing High-Speed Data Transfers References 788 Drill Problems 790 Exercises 792 xiii

8 xiv 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is 9 MEMORY, CPLDS, AND FPGAS Read-Only Memory Using ROMs for Random Combinational Logic Functions Internal ROM Structure Two-Dimensional Decoding Commercial ROM Types ROM Control Inputs and Timing ROM Applications 9.2 Read/Write Memory Static RAM Static-RAM Inputs and Outputs Static-RAM Internal Structure Static-RAM Timing Standard Static RAMs Synchronous SRAM 9.4 Dynamic RAM Dynamic-RAM Structure SDRAM Timing DDR SDRAMs 9.5 Complex Programmable Logic Devices Xilinx XC9500 CPLD Family Function-Block Architecture Input/Output-Block Architecture Switch Matrix 9.6 Field-Programmable Gate Arrays Xilinx XC4000 FPGA Family Configurable Logic Block Input/Output Block Programmable Interconnect References 859 Drill Problems 859 Exercises 860 INDEX 863