CSE477 VLSI Digital Circuits Fall Lecture 18/19: Datapath Design/Fast Adders

Transcription

1 CSE477 VLSI Digital Circuits Fall 2 Lecture 8/9: Datapath Design/Fast Adders [Adapted in part from Rabaey s Digital Integrated Circuits, Prentice Hall, 995] CSE477 L8 Datapath Design. Irwin&Vijay, PSU, 2

2 Major Components of a Computer Processor Devices Control Memory Input Datapath Output CSE477 L8 Datapath Design.2 Irwin&Vijay, PSU, 2

3 MIPS Pipelined Datapath IFetch Dec Exec Mem WB PC 4 Instruction Memory Read Address Add IF/Dec Read Addr Register Read Read Addr 2Data File Write Addr Write Data Read Data 2 Dec/Exec Shift left 2 Add ALU Exec/Mem Data Address Memory Write Data Read Data Mem/WB Sign 6 Extend 32 CSE477 L8 Datapath Design.3 Irwin&Vijay, PSU, 2

4 Bit-Sliced Approach Control Data In Register File Multiplexer Adder Shifter Bit 3 Bit 2 Bit Data Out Bit Tile identical processing elements CSE477 L8 Datapath Design.4 Irwin&Vijay, PSU, 2

5 Basic Building Blocks Datapath Execution units - Adder, multiplier, divider, shifter, comparator, etc. Register file and pipeline registers Multiplexors Control Finite state machines (PLA, ROM, random logic) Interconnect Switches, arbiters, buses Memory Caches, TLBs, DRAM, buffers CSE477 L8 Datapath Design.5 Irwin&Vijay, PSU, 2

6 The -bit Binary Adder A B C in C out S carry status A B C in -bit Full Adder (FA) S kill kill propagate propagate propagate propagate C out generate generate S = A B C in C out = A B v A C in v B C in (majority function) How can we use it to build a 32-bit adder? How can we modify it easily to build an adder/subtractor? How can we make it better (faster, lower power, smaller)? CSE477 L8 Datapath Design.6 Irwin&Vijay, PSU, 2

7 FA Gate Implementation A B C in A B C in C out S t t t2 t2 t t C out S CSE477 L8 Datapath Design.7 Irwin&Vijay, PSU, 2

8 XOR FA C in A B S C out 6 transistors CSE477 L8 Datapath Design.8 Irwin&Vijay, PSU, 2

9 CPL FA B B C in C in A!Sum A Sum B B C in C in A!C out B C in A C out B C in 28 transistors dual rail CSE477 L8 Datapath Design.9 Irwin&Vijay, PSU, 2

10 Delay Balanced FA B!B C in!p Identical Delays for Carry and Sum B p p A p A p!c out C in S C in!b A!p p!p!p Sum generation Carry generation Signal set-up 22 transistors CSE477 L8 Datapath Design. Irwin&Vijay, PSU, 2

11 A 32-bit Adder/Subtractor Ripple Carry Adder (RCA) built out of 32 FAs add/subt A C =C in -bit FA S Subtraction complement all subtrahend bits (xor gates) and set the low order carry-in RCA B B A A 2 C -bit FA S C 2 -bit FA S 2 advantage: simple logic, so small (low cost) B 2... C 3 disadvantage: slow (O(N)) and lots of glitching (so lots of energy consumption) A 3 C 3 -bit FA S 3 B 3 C 32 =C out CSE477 L8 Datapath Design. Irwin&Vijay, PSU, 2

12 Ripple Carry Adder (RCA) A 3 B 3 A 2 B 2 A B A B C out =C 4 FA FA FA FA C =C in S 3 S 2 S S T = O(N) worst case delay T adder T FA (A,B C out ) + (N-2)T FA (C in C out ) + T FA (C in S) Real Goal: Make the fastest possible carry path CSE477 L8 Datapath Design.2 Irwin&Vijay, PSU, 2

13 Mirror Adder -propagate -propagate A B B kill A B C in A!C out C in!sum A generate A B B A B C in C in B A C in A B C = AB + BCin +ACin 28 transistors S= ABCin + Co(A+B+Cin) CSE477 L8 Datapath Design.3 Irwin&Vijay, PSU, 2

14 The -bit Binary Adder A B C in C out S carry status A B C in -bit Full Adder (FA) S kill kill propagate propagate propagate propagate C out generate generate S = A B C in C out = A B v A C in v B C in (majority function) How can we use it to build a 32-bit adder? How can we modify it easily to build an adder/subtractor? How can we make it better (faster, lower power, smaller)? CSE477 L8 Datapath Design.4 Irwin&Vijay, PSU, 2

15 Mirror Adder Features The NMOS and PMOS chains are completely symmetrical with a maximum of two series transistors in the carry circuitry, guaranteeing identical rise and fall transitions if the NMOS and PMOS devices are properly sized. When laying out the cell, the most critical issue is the minimization of the capacitances at node!c out (four diffusion capacitances, two internal gate capacitances, and six next FA gate capacitances). The transistors connected to C in are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. CSE477 L8 Datapath Design.5 Irwin&Vijay, PSU, 2

16 Inversion Property A B A B C out FA C in C out FA C in S S!S (A, B, C in ) = S(!A,!B,!C in )!C out (A, B, C in ) = C out (!A,!B,!C in ) CSE477 L8 Datapath Design.6 Irwin&Vijay, PSU, 2

17 Exploiting the Inversion Property A 3 B 3 A 2 B 2 A B A B C out =C 4 FA FA FA FA C =C in S 3 S 2 S S odd cell even cell Minimizing the critical path the carry chain Need two flavors of FAs CSE477 L8 Datapath Design.7 Irwin&Vijay, PSU, 2

18 Fast Carry Chain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated g i = A i B i propagated p i = A i B i (sometimes use A i v B i ) annihilated (killed) k i =!A i!b i Giving a carry recurrence of C i+ = g i + C i p i C = g + p C C 2 = g + p g + p p C C 3 = g 2 + p 2 g + p 2 p g + p 2 p p C C 4 = g 3 + p 3 g 2 + p 3 p 2 g + p 3 p 2 p g + p 3 p 2 p p C CSE477 L8 Datapath Design.8 Irwin&Vijay, PSU, 2

19 Carry Chains On the average, the longest carry chain in adding N-bit numbers is of length log 2 N Experimental results verify this log 2 N worst case approximation and suggest that log 2 (.25N) is a better estimate The conclusion is that typical carry chains are usually quite short CSE477 L8 Datapath Design.9 Irwin&Vijay, PSU, 2

20 Manchester Carry Chain Adders Switches controlled by g i and p i!c i+ g i pi!c i clock Total delay of time to form the switch control signals g i and p i setup time for the switches signal propagation delay through n switches in the worst case CSE477 L8 Datapath Design.2 Irwin&Vijay, PSU, 2

21 Domino Manchester Carry Chain p 3 p 2 p p CLK C i, g 3 2 g 2 3 g 4 g 5 C i, CLK!(g 2 + p 2 g + p 2 p g + p 2 p p C i, )!(g + p C i, )!(g 3 + p 3 g 2 + p 3 p 2 g + p 3 p 2 p g + p 3 p 2 p p C i, )!(g + p g + p p C i, ) CSE477 L8 Datapath Design.2 Irwin&Vijay, PSU, 2

22 Four Bit-Sliced MC Adder clock,,,, g i p i g i p i g i p i g i p i C in CSE477 L8 Datapath Design.22 Irwin&Vijay, PSU, 2

23 Coping with Carries Carry-completion sensing (asynchronous) sense when carry is done (average carry length is O(log n)) Carry lookahead, conditional sum, Deferred carry assimilation (e.g., in multiplication) - carry save adders, signed digit adders CSE477 L8 Datapath Design.23 Irwin&Vijay, PSU, 2

24 Binary Adders synchronous word parallel adders ripple carry adders (RCA) T = O(N), A = O(N) carry prop min adders signed-digit fast carry prop residue adders adders adders T = O(), A = O(N) Manchester carry carry conditional carry carry chain select lookahead sum skip T = O(N) A = O(N) T = O(log N) A = O(N log N) T = O(N**/2), A = O(N) CSE477 L8 Datapath Design.24 Irwin&Vijay, PSU, 2

25 CSE477 VLSI Digital Circuits Fall 2 Lecture 9: Fast Adders [Adapted in part from Rabaey s Digital Integrated Circuits, Prentice Hall, 995] CSE477 L8 Datapath Design.25 Irwin&Vijay, PSU, 2

26 Review: A 32-bit Adder/Subtractor Ripple Carry Adder (RCA) built out of 32 FAs add/subt A C =C in -bit FA S Subtaction complement all subtrahend bits (xor gates) and set the low order carry-in RCA B B A A 2 C -bit FA S C 2 -bit FA S 2 advantage: simple logic, so small (low cost) B 2... C 3 disadvantage: slow (O(N) for N bit operands) and lots of glitching (so lots of energy consumption) B 3 A 3 C 3 -bit FA S 3 C 32 =C out CSE477 L8 Datapath Design.26 Irwin&Vijay, PSU, 2

27 Review: Fast Carry Chain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated g i = A i B i propagated p i = A i B i (sometimes use A i v B i ) annihilated (killed) k i =!A i!b i Giving a carry recurrence of C i+ = g i + C i p i C = g + p C C 2 = g + p g + p p C C 3 = g 2 + p 2 g + p 2 p g + p 2 p p C C 4 = g 3 + p 3 g 2 + p 3 p 2 g + p 3 p 2 p g + p 3 p 2 p p C CSE477 L8 Datapath Design.27 Irwin&Vijay, PSU, 2

28 Binary Adders synchronous word parallel adders ripple carry adders (RCA) T = O(N), A = O(N) carry prop min adders signed-digit fast carry prop residue adders adders adders T = O(), A = O(N) Manchester carry carry conditional carry carry chain select lookahead sum skip T = O(N) A = O(N) T = O(log N) A = O(N log N) T = O(N**/2) A = O(N) CSE477 L8 Datapath Design.28 Irwin&Vijay, PSU, 2

29 Carry-Skip (Carry-Bypass) Adder A 3 B 3 A 2 B 2 A B A B C 3 FA FA FA FA C i, C o,3 S 3 S 2 S S BP = p p p 2 p 3 Block Propagate Idea: If (p and p and p 2 and p 3 = ) then C o,3 = C i, else block kills carry or generates carry internally CSE477 L8 Datapath Design.29 Irwin&Vijay, PSU, 2

30 Carry-Skip Chain Implementation carry-out block carry-out BP block carry-in BP p 3 p 2 p p!c o,3 C i, g 3 g 2 g g BP CSE477 L8 Datapath Design.3 Irwin&Vijay, PSU, 2

31 4-bit Block Carry-Skip Adder bits 2 to 5 bits 8 to bits 4 to 7 bits to 3 Setup Setup Setup Setup Carry Propagation Carry Propagation Carry Propagation Carry Propagation C i, Sum Sum Sum Sum Worst-case delay carry from bit to bit 5 = carry generated in bit, ripples through bits, 2, and 3, skips the middle two groups (B = group size in bits), ripples in the last group from bit 2 to bit 5 T add = t setup + B t carry + ((N/B) -2) t skip +B t carry + t sum CSE477 L8 Datapath Design.3 Irwin&Vijay, PSU, 2

32 Optimal Block Size Assuming one stage of ripple has the same delay as one skip logic stage (where B is the number of bits in a block and for N bit operands) T CSkA = (B-) (N/B-2) + (B-) in block OR gate skips in last block = 2B + N/B stages So the optimal block size is dt CSkA /db = (N/2) **/2 = B opt And the optimal time is Optimal T CSkA = 2(2N**/2) CSE477 L8 Datapath Design.32 Irwin&Vijay, PSU, 2

33 One Level Variable Carry-Skip Adder c out c in CSE477 L8 Datapath Design.33 Irwin&Vijay, PSU, 2

34 Variable Carry-Skip Addition Clearly, a carry that is generated in, or absorbed by, one of the inner blocks travels a shorter distance through the skip blocks. So can allow more ripple stages for inner carries without increasing the overall delay Bt- Bt-2 B B skip one fewer skip one fewer skip ripple carry path carry path 2 carry path 3 CSE477 L8 Datapath Design.34 Irwin&Vijay, PSU, 2

35 Optimal Variable Block Sizes B B+ (B+K)/2 - (B+K)/2 - B+ B So the total number of bits in the K blocks is B = N/K - K/4 + /2 Giving an adder delay of T VSkA = 2N/K + K/2-2.5 So the optimal number of blocks is dt VSkA /dk = 2 (N**/2) = t opt And optimal time is Optimal T VSkA = 2 (N**/2) CSE477 L8 Datapath Design.35 Irwin&Vijay, PSU, 2

36 Multilevel Carry-Skip Addition What about allowing a carry to skip over several blocks at once? cout cin three skips one skip skip level skip level 2 AND of the first level skip signals (BP s) CSE477 L8 Datapath Design.36 Irwin&Vijay, PSU, 2

37 Carry-Skip Adder Comparisons RCA CSkA VSkA 2 8 bits 6 bits 32 bits 48 bits 64 bits CSE477 L8 Datapath Design.37 Irwin&Vijay, PSU, 2

38 Carry-Select Adder Setup P,G "" "" Carry Propagation "" "" Carry Propagation C o,k- Multiplexer C o,k+3 Sum Generation Carry Vector CSE477 L8 Datapath Design.38 Irwin&Vijay, PSU, 2

39 Carry-Select Adder: Critical Path Bit -3 Bit 4-7 Bit 8- Bit 2-5 Setup Setup Setup Setup "" "" Carry "" "" Carry "" "" Carry "" "" Carry "" "" Carry "" "" Carry "" "" Carry "" "" Carry Multiplexer Multiplexer Multiplexer Multiplexer C i, C o,3 C o,7 C o, C o,5 Sum Generation Sum Generation Sum Generation Sum Generation S -3 S 4-7 S 8- S 2-5 CSE477 L8 Datapath Design.39 Irwin&Vijay, PSU, 2

40 Linear Carry-Select Adder Bit -3 Bit 4-7 Bit 8- Bit 2-5 Setup Setup Setup Setup () "" () "" Carry "" "" Carry "" "" Carry "" "" Carry C i, "" "" Carry (5) (5) Multiplexer "" "" Carry (5) "" "" Carry (5) "" "" Carry (5) (6) (7) (8) Multiplexer Multiplexer Multiplexer (9) Sum Generation Sum Generation Sum Generation Sum Generation S -3 S 4-7 S 8- S 2-5 () CSE477 L8 Datapath Design.4 Irwin&Vijay, PSU, 2

41 Square Root Carry-Select Adder Bit - Bit 2-4 Bit 5-8 Bit 9-3 Bit 4-9 Setup Setup Setup Setup () "" Carry "" () "" "" Carry "" "" Carry "" "" Carry C i, "" Carry "" Carry "" Carry "" Carry "" "" "" "" (3) (3) (4) (5) (6) (4) (5) (6) (7) Multiplexer Multiplexer Multiplexer Multiplexer (7) Mux (8) Sum Generation Sum Generation Sum Generation Sum Generation Sum S - S 2-4 S 5-8 S 9-3 S 4-9 (9) M M is number of bits in first stage; 2N^/2 is number of stages CSE477 L8 Datapath Design.4 Irwin&Vijay, PSU, 2

42 Carry Lookahead Adder Carry recurrence C i+ = g i + C i p i C = g + p C C 2 = g + p g + p p C C 3 = g 2 + p 2 g + p 2 p g + p 2 p p C C 4 = g 3 + p 3 g 2 + p 3 p 2 g + p 3 p 2 p g + p 3 p 2 p p C C 5 = g 4 + p 4 g 3 + p 4 p 3 g 2 + p 4 p 3 p 2 g + p 4 p 3 p 2 p g + p 4 p 3 p p 2 p C C 6 = g 5 + p 5 g 4 + p 5 p 4 g 3 + p 5 p 4 p 3 g 2 + p 5 p 4 p 3 p 2 g + p 5 p 4 p 3 p 2 p g + p 5 p 4 p 3 p 2 p p C... CSE477 L8 Datapath Design.42 Irwin&Vijay, PSU, 2

43 Carry Lookahead Concept A,B A,B A N-,B N-... all carries are determined directly from the input bits C i, P C i, P C i,n- P N-... CSE477 L8 Datapath Design.43 Irwin&Vijay, PSU, 2

44 Carry Lookahead Topology V DD G 3 G 2 G G C i, Co,3 P P P 2 P 3 CSE477 L8 Datapath Design.44 Irwin&Vijay, PSU, 2

45 Logarithmic Time Adder Approach Operator where (g, p) (g, p ) = (g (p g ), p p ) Can prove (by induction) that (G i, P i ) = (g, p ) if i = (g i, p i ) (G i-, P i- ) if i N- And, since the operator, is associative, the computation of the (G i, P i ) s can be done in any order. CSE477 L8 Datapath Design.45 Irwin&Vijay, PSU, 2

46 T = log 2 N - 2 A = 2log 2 N T = log 2 N Brent-Kung (Log Time) Adder g 5 p 5 g 4 p 4 g 3 p 3 g 2 p 2 g p g p g 9 p 9 g 8 p 8 g 7 p 7 g 6 p 6 g 5 p 5 g 4 p 4 g 3 p 3 g 2 p 2 g p g p C Parallel Prefix Computation c 6 c 5 c 4 c 3 c 2 c c c 9 c 8 c 7 A = N/2 c 6 c 5 c 4 c 3 c 2 c CSE477 L8 Datapath Design.46 Irwin&Vijay, PSU, 2

47 T = log 2 N - 2 A = 2log 2 N T = log 2 N Brent-Kung (Log Time) Adder g 5 p 5 g 4 p 4 g 3 p 3 g 2 p 2 g p g p g 9 p 9 g 8 p 8 g 7 p 7 g 6 p 6 g 5 p 5 g 4 p 4 g 3 p 3 g 2 p 2 g p g p C Parallel Prefix Computation c 6 c 5 c 4 c 3 c 2 c c c 9 c 8 c 7 A = N/2 c 6 c 5 c 4 c 3 c 2 c CSE477 L8 Datapath Design.47 Irwin&Vijay, PSU, 2

48 PDP of Different Adders RCA MCCA CSkA VSkA CSlA CLA BKA ELMA 8 bits 6 bits 32 bits 48 bits 64 bits From Nagendra, 996 CSE477 L8 Datapath Design.48 Irwin&Vijay, PSU, 2

49 Next Lecture and Reminders Next lecture Multipliers/Shifters - Reading assignment Rabaey, CSE477 L8 Datapath Design.49 Irwin&Vijay, PSU, 2

50 Next Lecture and Reminders Next lecture Fast adders - Reading assignment Rabaey, CSE477 L8 Datapath Design.5 Irwin&Vijay, PSU, 2