ASM and Register Transfer Level

Transcription

1 ASM and Register Transfer Level

2 Overview System design must be modular Easier to represent designs with system-level blocks Register transfer level represents transfers between clocked system registers Shifts, arithmetic, logic, etc. Algorithmic state machine Alternate approach to representing state machines Status signals from datapath used for control path Algorithmic state machine chart shows flow of computation

3 System-level Design Difficult to represent a design with just one state machine A series of control and data paths used to build computer systems Helps simplify design and allow for design changes Main Memory Processor Keyboard Disk

4 Registers and Data Operations Activity and performance in computers defined on register-to-register paths Digital system at register transfer level specified by three components The set of registers in the system Operations to be performed on registers Control that is applied to registers and sequence of operations Function

5 Representation of Register Transfer Flow Arrow indicates transfer from one register to another R2 R Conditional statements can help in selection If (T = ) then R2 R Clock signal is not generally included in register transfer level statement Sequential behavior is implied Multiple choices also possible If (T = ) then (R2 R, R2 R2) How could these statements be implemented in hardware?

6 Other representative RTL operations Addition R R + R2 Increment R3 R3 + Shift right R4 R4 Clear R5 Transfer doesn't change value of data begin moved How could these statements be implemented in hardware?

7 Algorithmic State Machines (ASM) Flowchart specifies a sequence of procedural steps and decision steps for a state machine Translates word description into a series of operations with conditions for execution Allows for detailed description of control and datapath

8 Algorithmic State Machines State Box ASM describes operation of a sequential circuit ASM contains three basic elements State box Decision box Condition box State box indicates an FSM state Box also indicates operation to be performed Binary code and state name also included

9 Decision Box Describes the impact of input on control system Contains two exit paths which indicate result of condition More complicated conditions possible Implemented in hardware with a magnitude comparator

10 Conditional Box Indicates assignments following a decision box Generally indicates data transfer

11 ASM Block Paths exist between state boxes Each state box equivalent to one state

12 ASM Block Equivalent to State Diagram

13 Concept of the State Machine Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 's Reset Even [] Present State Even Even Odd Odd Input Ne xt Stat e Even Odd Odd Even Output Symbolic State Transition Table Odd [] State Diagram Present State Input Next State Output Encoded State Transition Table Note: Present state and output are the same value Moore machine

14 ASM for Odd Parity Checker Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 's Reset Even [] Even Out Odd [] In = State Diagram Odd Out In =

15 Algorithmic State Machines (ASMs) State_Name Moore outputs Input Mealy outputs (a) (b) (c) Figure 8.42

16 ASM Representation of a Mealy Machine z = A X z = / X/Y A / / / / / C B B z = (b) X z = z = C z = Figure 8.43 X (a)

17 ASM Representation of a Moore Machine A z = X B z = A/ B/ X C/ (b) C z = X Figure 8.44 (a)

18 Eight-Bit Two s Complementer ASM -- Example 8.9 z = A Look for first bit x z = z = B Complement remaining bits z = x Figure 8.45

19 Design Example: Binary Multiplier Two basic approaches implementing the control unit Hardwired control - less costly - faster operation speeds Microprogrammed control - many complex instructions

20 Design Example: Binary Multiplier (2) Binary Multiplier Multiplication of two unsigned binary numbers Hand multiplication example Need n binary a dditions shift FIGURE 8-4 Hand Multiplication Example

21 Design Example: Binary Multiplier (3) Hardware multiplication example

22 Design Example: Binary Multiplier (4) Multiplier Datapath n operations occur, n- down through external contr ol input 4 Stores the Cout, Reset to during the right shift FIGURE 8-6 Block Diagram for Binary Multiplier

23 S IDLE Start= Register A COUNTER P S CLEAR R, LOAD A,B,P Cout ADDER Register B S2 C Register R Left-half Register R Right-half B()= RLß RL+A P= S3 SHR B,R, C DEC P

24 P.S Start= N.S Output S() Start= S() S() Start= S() S() Dn t Care S2() Clear R, Load A,B,P S2() B()= S3() Load RL S2() B()= S3() S3() Not(P=) S2() SHR B,R,C, DEC P S3() P= S() SHR B,R,C, DEC P S S S2 IDLE Start= CLEAR R, LOAD A,B,P Clock FF D FF D DECODER 2 3 SHR B,R, C DEC P B()= Load RL CLEAR R, LOAD A,B,P P= S3 B()= SHR B,R, C DEC P RLß RL+

25 P.S(DD) Start= N.S Output S() Start= S() S() Start= S() S() Dn t Care S2() Clear R, Load A,B,P S2() B()= S3() Load RL P(3) P(2) P() P() (P=)=P().P().P(2).P(3) =(P()+P()+P(2)+P(3)) (P=) =P()+P()+P(2)+P(3) S2() B()= S3() S3() Not(P=) S2() SHR B,R,C, DEC P S3() P= S() SHR B,R,C, DEC P Q/Q Start Q/Q Not(P=) D=Q Q.Start+Q.Q D=Q.Q+Q.Q +Q.Q.Not(P=)

26 Register A Register B COUNTER P DECODER 2 3 SHR B,R, C DEC P B()= CLEAR R, LOAD A,B,P C Register R Register R Left-half Right-half REGISTER R