CSE2102 Digital Design II - Topics CSE Digital Design II

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1 CSE2102 Digital Design II - Topics CSE Digital Design II 6 - Microprocessor Interfacing - Memory and Peripheral Dr. Tim Ferguson, Monash University. AUSTRALIA. Tel: FAX: WWW: timf/ Clayton Office: Building 63, Room G08 1. Hardware Design of a Simple CPU. 2. Microprogrammed Implementation of Controller ASM. 3. Numerical Representation and Algorithms. 4. Multiplication and Multiplier Design. 5. VHDL for Digital System Design and Description. 6. Microprocessor Interfacing - Memory and Peripheral. 7. Introduction to Microcontroller and the MC68HC11 High Performance MCU. 8. Revision. Memory and peripheral interfacing is an important topic in practical applications of microprocessor systems. This topic introduces some general concepts in terms of memory and peripheral device interfacing. Note: These slides are based on a set created by Dr. Bin Qiu. 2 The discussion is mainly concerned with the hardware aspects. 6.1 Memory Interface Analysis of access timing Timing relationship diagrams are normally given in the data sheet of a memory or microprocessor device. The following is an example of a timing diagram. For a more practical case study, we have a close look at the timing diagrams of the Motorola MC68HC11 processor, and a Motorola memory device, MCM We focus on whether or not these two chips can be made to interface with one another. The microprocessor/controller has 8/16 bit data/address. The data bus is multiplexed with the lower 8 bit of the address bus. The clock cycle is about 500ns and there is a single R/W control line. The memory chip has 2K 8 bits, and its access time is 200ns. It seems that the memory chip can provide a satisfactory service to the microprocessor since it has a faster access time. The result is different after the examination of timing diagrams. CPU Memory CPU Memory Write cycle timing Read cycle timing 3 Figure 1: Example timing diagram. During a write cycle, the CPU should give the memory enough time to latch the data, and vise versa during the read cycle. 4

2 Write timing E - Bus clock (1/4 crystal) RW - Read/Write line A - Address D - Data AS - Address strobe The easiest way to arrange the signals are as follows: a) The E clock signal is inverted to serve as CE - latch on rising edge. b) The write enable signal W can be made using CE and RW. (a) MC68HC11 (b) MCM Figure 2: Write cycle timing diagram. As a result, the write timing interface is OK. 6 Read timing With signal arrangements the same as write timing, the read timing analysis goes as follows: 7 (a) MC68HC11 (b) MCM Figure 3: Read cycle timing diagram. 8 It can be seen from Figure 3 that both the setup and the hold time required by the MC68HC11 is not provided by the MCM As a result, the read timing is not up to the specifications. The problem can be solved by selecting different chips for interfacing or redesign signals such as CE.

3 Memory address decoding In a microcomputer system, the entire memory range is normally divided into different zones which represent RAM, ROM, I/O devices, etc. A 16-bit example is shown below, with 4Kb RAM, 16Kb ROM and 4Kb input/output address space. Depending on the usage of the address space, decoding schemes can be broadly classified as full decoding and partial decoding. Every single memory address is decoded in full decoding, resulting in a one address to one memory location mapping. In partial decoding, some address lines are not decoded, resulting in two or many addresses to one memory location mapping. Partial decoding reduces demands on decoding devices. A 16-bit example memory map Using the previous address space, an example decoding scheme with 4 modules of RAM and ROM, and a single I/O port is given as follows: 10 RAM decoding: 4 modules of 1Kx8 bits. The address for each module is given as: M-0: FF, M-1: FF, M-2: BFF, and M-3: 0C00-0FFF The decoding diagram is given on slide 11. ROM decoding: 4 modules of 4Kx8 bits. The address for each module is given as: M-0: C000-CFFF, M-1: D000-DFFF, M-2: E000-EFFF, M-3: F000-FFFF The decoding diagram is given on slide 12. The single I/O port is decoded with the highest four address bits and A2 only, just to distinguish it from the other address zones. Input port: 1000xxxxxxxxx1xx (A15-A0) Output port: 1000xxxxxxxxx0xx (A15-A0) E.g.: Read from 8004, 8005, 8FF4, 8xx4, etc. This is shown on slide

4 6.2 Input/Output Device Interface Input/Output devices can work in four general modes as illustrated below. MPU Initiated Device Initiated Unconditional transfer Conditional Interrupt Direct memory transfer * transfer * access (DMA) * Requires some exchanging of control device information between MCU and device (handshaking) CPU initiated, unconditional I/O transfer The I/O device is always assumed to be ready. Examples are LED displays as outputs and temperature sensors as inputs CPU initiated, conditional (polled) I/O transfer 13 The CPU reads I/O status to determine whether the device is ready for data transfer. A flow chart on the next page shows the sequence of steps involved in a polled I/O data transfer. 14 As an example, an external A/D converter is connected to a CPU using polled data transfer as shown on slide 16. The steps for data transfer are as follows: 1. The CPU issues a START pulse to begin the conversion of V A to its digital equivalent. 2. The CPU continually reads and tests the status of the A/D converter by polling, until BUSY is high. 3. The CPU reads in the A/D output data

5 6.2.3 I/O device initiated, interrupt transfer This is more efficient in terms of CPU time: The CPU serves I/O only when it is ready. The following points need to be noted for interrupt I/O transfer. 1. The main program needs to be paused and all parameters stacked. 2. The entrance address (vector) of the service routine can be fixed by the CPU or provided by the I/O device. 3. Interrupts can be software maskable or non-maskable, normally both exist in a system. 4. The handling of multiple interrupt sources can be dealt with by arranging priority of interrupts, or interrupt interrogation as illustrated below: I/O device initiated, direct memory access (DMA) transfer The previous interface techniques work well on slower I/O devices. DMA is suitable for bulk data transfer from internal memory to external fast I/O, or vise versa. The CPU is bypassed for DMA, when a DMA controller takes over control. Data can be moved between I/O and memory at a rate of one word per memory cycle. The steps of DMA are described as follows: The CPU initialises the DMA controller with a destination address and a count of the words that are to be transfered. When a peripheral is ready, it requests the DMA controller which halts the CPU. The CPU acknowledges its halted state after deactivating all bus lines. The DMA controller takes over the bus lines and transfers the specified amount of data from the peripheral to the specified memory address (i.e. a DMA transfer). The CPU is removed from the halted state on completion of the data transfer and regains the control of system buses. 20

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