Analysis of DC circuits with BJT (polarization)

Transcription

1 Session 12 Analysis of D circuits with JT (polarization) Electronic omponents and ircuits José A. Garcia Souto

2 D circuits with JT and polarization of transistors OJETIES Summarizing the operating regions and introducing the amplification (active) Active, ut-off, Saturation Analyzing basic JT circuits in D. Static characteristics and Load line. Understanding the need of polarization circuits Knowing and analyzing typical polarization circuits of transistors. ias (quiescent) point. 2

3 Amplification concept with JT I (ma) 60 SATURATES o UT-OFF o cc AMPLIFIES o G i 0 0,2 0,4 0,6 0,8 E() Small changes of i result in greater variation of o, thus providing gain o/i It should be around a bias point or quiescent point E-Q, E-Q 3

4 Superposition of D ias and Signal I is a continuous source that provides along with R a bias point (polarization) : v 0 v g I I (µa) E E I E I E E () A variable signal is introduced and it is added to + vg 4

5 Amplification focuses on Active region Datasheet E(on) E(sat) hfe E(sat) Search 547 in Region ase-emitter Junction ase-ollector Junction ut-off Reverse(OFF) Reverse Active Forward (ON) Reverse (Transistor Effect) Saturation Forward (ON) Forward (Saturated) Region onditions NPN Operation NPN ut-off E < E-ON o I 0 I0, IIE0 Active E-ON y E > E-SAT I hfe I [EE-ON] Saturation E-ON y E-SAT E E-SAT [EE-SAT] 5

6 Graphical D Analysis EXAMPLE R 100 Ω R 10 kω E(on) 0,7 E(sat) 0,2 hfe 100 I E I E I E ancel the signal (superposition) v g 0 Analyze the input Device Equation (Input haracteristic) ircuit Equation (Load line) Analyze the output Device Equation (Output haracteristic) ircuit Equation (Load line) 6

7 Input haracteristic and Load Line (I) I (µa) I E E(on) I E R E( on) E () Graphically haracteristic: Load line: i Analytically ( v v ) i i, E R > E(on) v v E E(on) v E E E + i R 7

8 Output haracteristic and Load Line (II) I (ma) 6 60 µa 5 50 µa I 4 I 40 µa 3 30 µa 2 20 µa 1 10 µa 0µA I E h FE I E I Graphically haracteristic: Load line : Analytically E () R ( v i ) i i, i E v R E > E(sat) i h FE v i E E + i R 8

9 D equivalent circuit: Analytically EXAMPLE R 100 Ω R 10 I Analyze the input Device Equation ircuit Equation E(on) 0,7 E(sat) 0,2 hfe 100 ase 3 10 I E E I E Analyze the output Device Equation ircuit Equation R 10 kω 9

10 Solution: D Analysis Analyze the input I > E(on) v Device Equation E E(on) ) I ircuit Equation v E + i R E Analyze the output E I E E > E(sat) Device Equation ircuit Equation i h FE v i E + i R E E(on) I R E( on) I h FE I E I R 10

11 ias circuits Set a stable operating point desensitized against the transistor parameters. Optimize the signal amplifier circuit. Separate bias circuit if necessary (signal A coupling). 11

12 Example Reasoning operating region alculate the voltage E alculate the current IE Derive the relationship between IE, I and I alculate the curents I and I alculate the voltage DATA 12 R RE 10 kω E(on) 0,7 E(sat) 0,2 hfe

13 Types of polarization circuits iasing with RE Practical circuit Lower sensitivity to the transistor current gain Stabilizes the bias point (quiescent point) against E, hfe, etc. 13

14 ase 1: iasing with R DATA: 5 10 R 50 kω R 3 kω RE 2 kω E(on) 0,7 E(sat) 0,2 hfe 100 Reasoning the operating region Indicate the value of E alculate the currents I, I e IE alculate the voltage E heck that is in active Recalculate if you change hfe

15 ase 2: iasing with RE DATA: 5 10 R 10 kω R 3 kω RE 2 kω E(on) 0,7 E(sat) 0,2 hfe 100 Reasoning the operating region Indicate the value of E alculate the current IE (you can neglect the base current I) alculate the currents I, I heck that I is negligible alculate the voltage E heck that the JT is in active Recalculate if you change hfe 200 Generalize if not negligible I (eg if R 50 kω) 15

16 iasing with current mirrors I O2 R2 Iref 10 I R 3 ref IO 1 I ref 16

17 Proposed exercise: urrent sources Zener ideal: Z 3,3 I Zmín 10 ma Transistor: Esat 0,2 Eon 0,7 β 270 I ref I L alculate I E, I, I and,, E, E, I Z. For R L 1 kω, calculate I y For R L 22 kω, calculate I y Plot the load lines (three cases). Maximum RL as a current source?. In the case R L 22 kω, calculate I, I Z Obtain the ratio I L /I ref Reason if I is negligible Obtain I ref There is the scale factor I 2 2 I 1 between both transistor. alculate o. 17