hochschule fu r angewandte wissenschaften hamburg Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik

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1 Counters Counters are used for many functions in digital systems, for example, counting the number of occurrences of an event, storing the address of the current instruction of a microprocessor or calculating the address of data words within a RAM. A counter is a kind of sequencer circuit that cycles through a specific series of states. The cycling will be governed by a master clock. Synchrous operation is provided by having all flip-flops clocked simultaneously so that the output changes coincide with each other: synchrous counter. The hardware of a counter can be partitioned into memory storage (edge triggered flip-flops) and combinational logic. Simple counters, which will be described first, have a clock signal as the only external input. If additional logic-steering is included such as reset, load and enable inputs, the counter will be an important subset of a finite state machine (FSM). One of the major concepts for understanding counters and their design is the term state. At any specific time step, the outputs of all flip-flops constitute the state. At the start of counter design a binary representation will be assigned to all states of the count sequence which can be described with a state diagram. A present state/next state table will be used to develop the next state forming logic. Counters are classified by the number of states which perform the sequence. A counter with n states is called modulo-n counter. Digital Circuits I -

2 . Modulo Counter No. Q Q Q Q Present state/next state table Q Q Q Q Q Q Q Q Q Q Q Q Digital Circuits I -

3 VHDL code of a modulo- counter entity MODCTR is port (PON,CLK : in BIT; QOUT: out BIT_VECTOR( downto )); end MODCTR; architecture COUNTER of MODCTR is signal QINT: BIT_VECTOR( downto ); begin SYN_COUNT:process (CLK, PON) begin if PON='' then QINT<="" after ns; elsif CLK='' and CLK'event then case QINT is when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when "" => QINT <= "" after ns; when others => QINT <= "" after ns; end case; end if; end process SYN_COUNT; QOUT <= QINT; -- avoid a buffer signal end COUNTER; Digital Circuits I -

4 . Modulo Up/Down Counter No. Q Q Q Q Present state/next state table with external input Q Q Q Q Q Q Q Q Digital Circuits I -

5 modulo- counter: VHDL code with addition and subtraction operators library IEEE; use IEEE.std_logic_.all; -- supports the data type std_logic use IEEE.std_logic_unsigned.all; -- supports addition/subtraction of vectors entity MODCTR is port (,PON,CLK : in BIT; QOUT: out BIT_VECTOR( downto ); CU, CD: out BIT); -- carry bits end MODCTR ; architecture COUNTER of MODCTR is signal QINT: STD_LOGIC_VECTOR( downto ); begin SYN_COUNT:process (CLK, PON) -- clock and asynchrous inputs begin if pon = '' then QINT <= "" after ns; elsif CLK='' and CLK'event then if = '' then QINT <= QINT "" after ns; --addition of bits else QINT <= QINT - after ns; -- subtraction of integer end if; end if; end process SYN_COUNT; QOUT <= TO_BITVECTOR(QINT); -- type conversion: casting CU <= '' after ns when ( = '' and QINT = ) else '' after ns; CD <= '' after ns when ( = '' and QINT = ) else '' after ns; end COUNTER; Digital Circuits I -

6 Simulation waveforms of a modulo- counter Carry outputs CU and CD are Mealy outputs because the external input has a direct effect on the carry bits. Digital Circuits I -

7 . Commercial Counters The variety of discrete counter ICs available is decreasing due to the rapid progress in hardware techlogy development. In the future most designs will be implemented with CPLD and/or FPGA logic. Texas Instruments (TI) offers two types of discrete counters from its AHC-(advanced highspeed) logic range. Nevertheless, it is important to understand the symbolic representation of counters, because it teaches the control dependencies and the priorities of counter functionality which are essential to kw and useful for many applications. Pin Depend. Function CLR_N CT= Reset of all flip-flops, asynchron. CLK C /,, Clock; count up if: LOAD_N = ENT =ENP= LOAD_N M M Counter load if LOAD_N = ; Count if LOAD_N = ENT G Count and carry RCO only if ENT= ENP G Count if ENP = D[:],D Data load input, synchrously RCO CT= Carry RCO = if counter content CT = Dependencies of a -bit programmable counter: xx Digital Circuits I -

8 Counter design guide lines Counters should be described with one clocked process to ensure that all outputs will be synthesized to flip-flops. The process description is recommended in order to have a code template which is different from descriptions of more complex finite state machines (FSM). Include and use IEEE libraries so that addition and subtraction operators can be applied. All additional outputs which depend on the counter state should be described with a second concurrent combinational process (carry or Asynchrous Reset? tri-state outputs). Q[:] set to zero Q[:] registered Rising Clock Edge? Delete Ripple Carry Out Q <= D Load? Q[:] registered Enable ENT and Q max? Enable? Q[:] increment Ripple Carry Out is 晦 Avoid reading the counter state within the clocked frame because usually it will be forgotten that the next counter state will be valid t before the end of process execution. Use decision charts to design counter functionality. The different priorities of asynchrous inputs and synchrous effects (clock edge dependent) of certain inputs can be shown easily. This simplifies the VHDL-coding! Digital Circuits I -8

9 Cascading of commercial counters (two hexadecimal digits) Digital Circuits I -9