Problem Session 5. Overview. Part 1: An S-R Latch. Part 2: A D Latch

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1 Problem Session 5 Overview The most basic element of binary storage is the latch, consisting of 2 cross-coupled NAND (or NOR) gates. The D latch, with a write enable input, is a rudimentary storage element. The D latch is employed in most forms of static memory, SRAM. In this problem session, you will work with Logisim to create a functioning 2x4 bank of SRAM using D latches. You will begin by building a D latch from an S-R latch. Part 1: An S-R Latch Objective: Implement an S-R Latch in Logisim. Build a cross-coupled NAND latch in Logisim. Connect inputs S and R to input pins, and outputs Q, and ~Q to output pins. Label all inputs and outputs. Experiment with your latch and draw (on paper) a truth table with inputs S, R and Q p and outputs Q and ~Q. Verify that your S-R Latch has the functionality discussed in class; identify the Not Allowed (NA), Set, Reset, and Memory modes of operation. Show your S-R latch and truth table to your instructor. Part 2: A D Latch Objective: Use your implementation of the S-R latch to create a D Latch in Logisim. Jan,

2 Build a D latch using your implementation of an S-R Latch along with two additional NAND gates and one inverter. The D Latch has 2 inputs: a data line and a write enable signal. Derive the truth table for the D latch with inputs WE and D, and outputs Q and ~Q. Verify that your D Latch has the functionality discussed in class, i.e., the latch is set when the write enable is 1 and it will hold that state after the write enable line goes to zero. Name your circuit D_Latch (rename main to be D_latch ) and save it to a file with the same name (i.e., D_Latch.circ ). Show your D latch and truth table to your instructor. Part 3: A 4-bit Word of Memory Objective: Use your implementation of a D-Latch to create a bank of four D latches. Import your D_Latch subcircuit into a new circuit file. To import a circuit into a Logisim project, go to Project > Load Library > Logisim Library and then navigate to the file containing the subcircuit that you want to import. You need to import the D latch file you created above. Jan,

3 Test the operation of your register. For testing, connect the output, Q, of each D latch to an output pin, and the inputs, WE and D, to input pins as shown above. Show your4-bit word of memory to your instructor, and demonstrate its functionality. Part 4: Controlling a 2x4 Bank of Memory Objective: Use a decoder to select the 4-bit word of memory to read or write. Begin by replicating your 4-bit word to produce two 4-bit words of memory as shown below. Alternatively you can download that design from this link (you ll also need the D latch that is used as a library file) and open it in Logisim. Now, use a 1x2 decoder to select the 4-bit word of memory to write: 1. Open the Plexers folder and insert a decoder in the schematic. (Optionally, select the decoder and set Include Enable to off in the lower-left corner of the Logisim window.) The decoder should have just one input select bit. For two words of memory, we can select between those two words with just one bit. The value of the select bit is the memory address. As noted in class, when we have 2 n words of memory we must have n address bits. 2. For each word of memory, introduce one AND gate. The output of that AND gate is the WE line for that word of memory. The input to the AND gate is one Decoder output and the WE signal, as shown below. This construction assures that both the WE signal and the memory address are used to select the word of memory that is written. Jan,

4 Show your bank of memory to your instructor, and demonstrate its functionality. Part 5: Writing to the Memory Bank Objective: Create common data inputs for both words of memory. Demonstrate that you can store different bit patterns in each word of memory. Jan,

5 Part 6: Reading from the Memory Bank Objective: Create a common output and use multiplexors to select the word that loads to output. Use (four) 2x1 multiplexers to select the 4-bit word of memory that writes to output: Open the Plexers folder and insert four MUXs into your schematic. (Optionally, select the MUX and set Include Enable to off in the lower-left corner of the Logisim window.) Each MUX should have just one select bit---the same select bit as the decoder---the memory address. Each MUX produces one bit of output by passing that bit from the selected word of memory. In other words, via the MUXs, the memory address is used to select the word that passes through to output one bit at a time. Demonstrate that you can store different bit patterns in each word and load the bit pattern from each word to output. Jan,