EKT 121/4 ELEKTRONIK DIGIT 1

Transcription

1 EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - Shift Registers -

2 Basic Shift Register Functions Consist of an arrangement of flip-flops. Important in applications involving storage and transfer of data (data movement) in digital system Used solely for storing and shifting data (s and s) entered into it from an external source and possesses no characteristic internal sequence of states. D flip-flops are widely use to store and move data

3 The flip-flop as a storage element. When a is on D, Q becomes a at triggering edge of CLK or remains a if already in the SET state When a is on D, Q becomes a at triggering edge of CLK or remains a if already in the RESET state

4 Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.)

5 Types of Shift Register. Serial In / Serial Out Shift Registers (SISO) (Daftar anjakan masukan siri / keluaran siri) 2. Serial In /Parallel Out Shift Registers (SIPO) (Daftar anjakan masukan siri / keluaran selari) 3. Parallel In / Serial Out Shift Registers (PISO) (Daftar anjakan masukan selari / keluaran siri) 4. Parallel In / Parallel Out Shift Registers (PIPO) (Daftar anjakan masukan selari / keluaran selari)

6 .Serial in / serial out shift register (SISO) Accepts data serially one bit at a time on a single line Produces the stored information on its output also in serial form

7 Four bits () being entered serially into the register.

8 Four bits () being serially shifted out of the register and replaced by all zeros.

9 Example : The states of 5-bit register for the specified data input and clock waveforms. Assume the register is initially cleared (all s)

10 Logic symbol : 8-bit serial in/serial out shift register. Indicates a shift register (SRG) with 8 bits capacity

11 2.Serial in / parallel out shift register (SIPO) Data bits entered serially (right-most bit first) Difference from SISO is the way data bits are taken out of the register in parallel. Output of each stage is available.

12 Example : The states of 4-bit register (SRG 4) for the data input and clocks waveforms. Assume the register initially contains all s

13 Example : The 74HC64 8-bit serial in/parallel out shift register. Logic diagram Logic Symbol

14 Sample timing diagram for a 74HC64 shift register.

15 3.Parallel In / Serial Out Shift Registers (PISO) The bits entered simultaneously into their respective stages on parallel lines. Produces the stored information on its output in serial form

16 Example : A 4-bit parallel in/serial out shift register. Data input lines Allows 4 bits data to load in parallel into register. Logic diagram When SHIFT/LOAD is LOW, gates G,G2,G3 are enabled, allow each data bit to be applied to D input of its respective flip-flop. Flip-flop D= will SET and D= will RESET storing 4 bit storage simultaneously. When SHIFT/LOAD is HIGH, gates G,G2,G3 are disabled, G4,G5,G6 are enabled allow data bit shift to right from one stage to the next. OR gates allow normal shifting operation or parallel data-entry operation Logic depending symbolon which AND gates are enabled

17 Example : The data-output waveform for a 4-bit register with parallel input data and the Clock.. Clock pulse, parallel data = is loaded making Q3 a. 2. Clock pulse2, from Q2 shifted onto Q3. 3. Clock pulse3, shifted onto Q3. 4. Clock pulse4, last bit data () is shifted onto Q3. 5. Clock pulse5, all data bits have been shifted out. and only s remain in the register.

18 Example : The 74HC65 8-bit parallel load shift register. Refer to page 542 on your text book

19 Sample timing diagram for a 74HC65 shift register. Refer to page 542 on your text book

20 4.Parallel in/parallel out shift registers (PIPO)

21 Example : The 74HC95 4-bit parallel access shift register. Refer to page 544 on your text book for details.

22 Sample timing diagram for a 74HC95 shift register. Refer to page 544 on your text book for details.

23 Bidirectional Shift Register Data can be shifted left/right Can be implemented by using a gating logic that enables the transfer of data bit from one stage to next stage to the right or to the left depending on level of control line. 74HC94 is an bidirectional universal shift register

24 Four-bit bidirectional shift register.

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26 74HC94 Universal shift register has both serial and parallel input and output capability.

27 Sample timing diagram for a 74HC94 shift register.

28 Shift Register Counters Basically a shift register with the serial output connected back to the serial input to produce special sequences. Classified as a counter because they exhibit specific sequence of states. Two most common types of shift register: ) Johnson Counter 2) Ring Counter

29 .Johnson Counter In a Johnson counter the complement of the output of the last flip-flip is connected back to the D input of the first flipflop. Feedback arrangement produces a characteristic sequence of states. Generally, Johnson counter will produce a modulus of 2n, where n is a number stages of counter.

30 Four-bit and 5-bit Johnson counters.

31 Q 3 Q 2 Q Q Clock pulse Four-bit Johnson Sequence

32 Timing sequence for a 4 bit Johnson counter

33 7 8 Q Q 4 Q 2 Q Q Clock pulse Five-bit Johnson Sequence

34 Timing sequence for a 5 bit Johnson counter

35 2.Ring Counter A ring counter utilizes one flip-flop for each states in its sequence. Advantage : Decoding gates are not required. A logic diagram for a -bit ring counter as follow

36 Ten-bit ring counter sequence Q 9 Q 8 Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q Q Clock pulse

37 The initial state is

38 Shift Register Applications Examples of Shift Register applications : Time delay Serial-to-Parallel Data Converter Universal Asynchronous Receiver Transmitter (UART) Keyboard encoder

39 .The shift register as a time-delay device. SISO shift register can be used to provide a time delay from input to output that is the function of number of stages (n) in register and clock frequency. Cascading shift register will increase time delay and decreased by taking the output from successively low stages in register (if available)

40 Example : A ring counter using a 74HC95 shift register.

41 Timing diagram showing two complete cycles of the ring counter when it is initially preset to

42 2.Simplified logic diagram of a serial-to-parallel converter. Logic diagram

43 Serial data format.

44 Timing diagram illustrating operation of serial-to-parallel data converter

45 3. Universal Asynchronous Receiver Transmitter (UART) Receives data in serial format, converts data to parallel format and place them on the data bus. Also accepts parallel data from data bus, converts data to serial format and transmits them to external device.

46 Basic UART block diagram

47 4.Simplified keyboard encoding circuit.

48 Next week Introduction to Programmable Logic Devices (PLD) -Thank you -