AOI Logic Implementation. Digital Electronics

Similar documents
CSEE 3827: Fundamentals of Computer Systems. Standard Forms and Simplification with Karnaugh Maps

Boolean Algebra Part 1

Karnaugh Maps & Combinational Logic Design. ECE 152A Winter 2012

Boolean Algebra. Boolean Algebra. Boolean Algebra. Boolean Algebra

Simplifying Logic Circuits with Karnaugh Maps

Chapter 2: Boolean Algebra and Logic Gates. Boolean Algebra

Karnaugh Maps. Circuit-wise, this leads to a minimal two-level implementation

CSE140: Midterm 1 Solution and Rubric

United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1

BOOLEAN ALGEBRA & LOGIC GATES

Digital circuits make up all computers and computer systems. The operation of digital circuits is based on

Combinational circuits

Basic Logic Gates Richard E. Haskell

CH3 Boolean Algebra (cont d)

Logic Reference Guide

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

Unit 3 Boolean Algebra (Continued)

CSE140: Components and Design Techniques for Digital Systems

Boolean Algebra (cont d) UNIT 3 BOOLEAN ALGEBRA (CONT D) Guidelines for Multiplying Out and Factoring. Objectives. Iris Hui-Ru Jiang Spring 2010

Karnaugh Maps (K-map) Alternate representation of a truth table

Logic in Computer Science: Logic Gates

Gates, Circuits, and Boolean Algebra

Introduction. The Quine-McCluskey Method Handout 5 January 21, CSEE E6861y Prof. Steven Nowick

Two-level logic using NAND gates

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc

2 : two cube. 5 : five cube. 10 : ten cube.

COMBINATIONAL CIRCUITS

Gates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction

Binary Adders: Half Adders and Full Adders

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

3.Basic Gate Combinations

2.0 Chapter Overview. 2.1 Boolean Algebra

Elementary Logic Gates

CHAPTER 3 Boolean Algebra and Digital Logic

DESIGN OF GATE NETWORKS

SOLUTIONS MANUAL DIGITAL DESIGN FOURTH EDITION M. MORRIS MANO California State University, Los Angeles MICHAEL D.

Question 2: How do you solve a matrix equation using the matrix inverse?

COMPUTER SCIENCE. Paper 1 (THEORY)

Let s put together a Manual Processor

Lecture 4: Binary. CS442: Great Insights in Computer Science Michael L. Littman, Spring I-Before-E, Continued

Lecture 5: Gate Logic Logic Optimization

C H A P T E R. Logic Circuits

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.

Section 1. Finding Common Terms

MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.

Combinational Logic Design Process

FORDHAM UNIVERSITY CISC Dept. of Computer and Info. Science Spring, Lab 2. The Full-Adder

Switching Algebra and Logic Gates

DEPARTMENT OF INFORMATION TECHNLOGY

Combinational Logic Design

Systems I: Computer Organization and Architecture

Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards

ENGI 241 Experiment 5 Basic Logic Gates

Negative Integer Exponents

AMC 10 Solutions Pamphlet TUESDAY, FEBRUARY 13, 2001 Sponsored by Mathematical Association of America University of Nebraska

Class One: Degree Sequences

Understanding Logic Design

Digital Electronics Detailed Outline

1.4. Arithmetic of Algebraic Fractions. Introduction. Prerequisites. Learning Outcomes

Figure 8-1 Four Possible Results of Adding Two Bits

exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576

Click on the links below to jump directly to the relevant section

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

DERIVATIVES AS MATRICES; CHAIN RULE

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language

EG1108: Electrical Engineering

Chapter 7 Memory and Programmable Logic

MATH Fundamental Mathematics IV

Counters and Decoders

To Evaluate an Algebraic Expression

Binary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders

FORDHAM UNIVERSITY CISC Dept. of Computer and Info. Science Spring, The Binary Adder

earlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder.

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell

Lecture 2 Matrix Operations

Philadelphia University Faculty of Information Technology Department of Computer Science Semester, 2007/2008.

In the above, the number 19 is an example of a number because its only positive factors are one and itself.

Base Conversion written by Cathy Saxton

C H A P T E R Regular Expressions regular expression

December 4, 2013 MATH 171 BASIC LINEAR ALGEBRA B. KITCHENS

Factoring. Factoring Monomials Monomials can often be factored in more than one way.

A Course Material on DIGITAL PRINCIPLES AND SYSTEM DESIGN

Sample Test Questions

RULE 1: Additive Identity Property

Vector Notation: AB represents the vector from point A to point B on a graph. The vector can be computed by B A.

Solving Systems of Linear Equations Using Matrices

SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks

BINARY CODED DECIMAL: B.C.D.

Series and Parallel Circuits

Chapter 3. if 2 a i then location: = i. Page 40

Sistemas Digitais I LESI - 2º ano

Module 2. DC Circuit. Version 2 EE IIT, Kharagpur

1.3 Polynomials and Factoring

COMPUTER SCIENCE 1999 (Delhi Board)

Factoring a Difference of Two Squares. Factoring a Difference of Two Squares

Using Logic to Design Computer Components

Sect Greatest Common Factor and Factoring by Grouping

Sum-of-Products and Product-of-Sums expressions

Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots

Transcription:

AOI Logic Implementation Digital Electronics

AOI Logic Implementation This presentation will demonstrate how to: 1) Design an AOI logic circuit from a Sum-Of- Products (SOP) logic expression. OUT A B B C EQUALS Logic Expression AOI Logic Circuit 2

AOI Logic Implementation This presentation will also demonstrate how to: 2) Design an AOI logic circuit from a Product-Of- Sums (POS) logic expression. OUT A B B C EQUALS Logic Expression AOI Logic Circuit 3

Sum-Of-Products (SOP) Sum-of-Products is one of two ways to create a logic expression. A logic expression, in SOP form, shows all of the input combinations that produce a logic 1 output. These combinations of input variables are known as Minterms. 4

Sum-Of-Products (SOP) In a Sum-of-Products expression the Minterms are summed (OR ed) together. SOP expressions can easily be implemented as a set of AND gates feeding into a single OR gate. Example: F 2 A B CD B CD A B 5

Designing AOI SOP Logic Circuits Three (3) Design Steps 1) Implement each Minterm in the logic expression with an AND gate with the same number of inputs as there are variables in the Minterm. (i.e., AB = 2 input gate, ABC = 3 input gate, ABCD = 4 input gate, etc.) 6

Designing AOI SOP Logic Circuits Three (3) Design Steps 2) OR together the outputs of the AND gates to produce the logic expression. 3) If necessary, gates can be cascaded to create gates with more inputs. 7

Example #1: AOI Implementation SOP Design an AOI Logic Circuit for the SOP logic expression shown below. F 2 A B CD B CD A B 8

Example #1: AOI Implementation SOP Solution: F 2 A B CD B CD A B 9

Example #1: AOI Implementation SOP Unfortunately, in this class, we only have access to (2) input OR gates and (2) & (3) input AND gates. Limiting your design to these gates, redesign the AOI Logic Circuit for the SOP expression in the previous example. 10

Example #2: AOI Implementation SOP Solution: Redesigned using 2-3 input gates only. 11

12

Product-Of-Sums (POS) Product-of-Sum (POS) is another way to create a logic expression. A logic expression, in POS form, is the complement of the SOP form. 13

Product-Of-Sums (POS) A logic expression, in POS form, shows all the input combinations that produce a logic 0 output. These combinations of input variables are known as Maxterms. 14

Product-Of-Sums (POS) In a Product-Of-Sums expression, the Maxterms are multiplied (AND ed) together. POS expressions can be implemented as a set of OR gates feeding into a single AND gate. F 4 Example: W X Y Z W X Y W Z 15

Designing AOI POS Logic Circuits Three (3) Design Steps 1. Implement each Maxterm in the logic expression with an OR gate with the same number of inputs as there are variables in the Maxterm. (i.e., A+B = 2 input gate, A+B+C = 3 input gate, A+B+C+D = 4 input gate, etc.) 16

Designing AOI POS Logic Circuits Three (3) Design Steps 2. AND together the outputs of the OR gates to produce the logic expression. 3. If necessary, gates can be cascaded to create gates with more inputs. 17

POS Logic Expression From Truth Table Write the Maxterm adjacent to every row in the truth table that contains a zero in the output column. Write the Product of Sums (POS) logic expression by multiplying together all of the Maxterms. Example: Write the POS logic expression for the output F 5 in the truth table below. X Y Z F 5 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 X+Y+Z X+Y +Z X +Y+Z X +Y +Z F 5 = (X+Y+Z) (X+Y +Z) (X +Y+Z ) (X +Y +Z ) Maxterms POS Logic Expression 18

Another example: Truth Table for AOI POS Logic Circuits A B C F 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 Maxterms (A+B) (A+B +C) (A +B ) Truth Table for POS is the complement of SOP Maxterms are zero output levels Input levels are reversed (eg. a zero is X and a 1 is X ) Inputs are summed to make the maxterm Maxterms are multiplied to get the logic statement F 1 = (A+B) (A+B +C) (A +B ) POS Logic Expression In this case, SOP logic is simpler: F 1 = A BC + AB C 19

Example #3: AOI Implementation POS Design an AOI Logic Circuit for the POS logic expression shown below. F 4 W X Y Z W X Y W Z 20

Example #3: AOI Implementation POS Solution W X Y Z W X Y W Z F 4 21

Example #4: AOI Implementation POS Limiting your design to only (2) input OR gates and 2-3 input AND gates, redesign the AOI Logic Circuit for the POS logic expression in the previous example. 22

Example #4: AOI Implementation POS Solution 23

The End! 24