DESIGN OF GATE NETWORKS

Transcription

1 DESIGN OF GATE NETWORKS DESIGN OF TWO-LEVEL NETWORKS: and-or and or-and NETWORKS MINIMAL TWO-LEVEL NETWORKS KARNAUGH MAPS MINIMIZATION PROCEDURE AND TOOLS LIMITATIONS OF TWO-LEVEL NETWORKS DESIGN OF TWO-LEVEL nand-nand and nor-nor NETWORKS PROGRAMMABLE LOGIC: plas and pals.

2 DESIGN OF TWO-LEVEL NETWORKS 2 IMPLEMENTATION: Level (optional) not GATES Level 2 and GATES Level 3 or GATES LITERALS (uncomplemented and complemented variables) not GATES (IF NEEDED) PRODUCTS: and gates SUM: or gate MULTIOUTPUT NETWORKS: ONE or GATE USED FOR EACH OUTPUT PRODUCT OF SUMS NETWORKS - SIMILAR

3 MODULO-64 INCREMENTER 3 Input: 0 x 63 Output: 0 z 63 Function: z = (x + ) mod z z RADIX-2 REPRESENTATION if (x i = and there exists j < i such that x j = 0) z i = or (x i = 0 and x j = for all j < i) 0 otherwise z 5 = x 5 (x 4 x 3 x 2 x x 0) x 5x 4 = x 5 x 4 x 5 x 3 x 5 x 2 x 5 x x 5 x 0 x 5x 4 z 4 = x 4 x 3 x 4 x 2 x 4 x x 4 x 0 x 4 z 3 = x 2 x x 0 x 3 z 2 = x x 0 x 2 z = x 0 x z 0 = x 0

4 x 5 x' 5 x 4 4 x' 3 x 4 x' 4 x' 2 x' 3 x' z 4 x' 2 x' x' 0 x' 0 x' 4 x2 x x0 x 5 x' 4 x' 2 x' x' 3 z 3 x' 2 x' z 5 x2 x x0 x' 0 x' 3 x2 x x0 x' 0 x 4 x' 5 x' 0 x' x' 0 x' 2 z 2 z x' z 0 Figure 5.: not-and-or MODULO-64 INCREMENTER NETWORK.

5 UNCOMPLEMENTED AND COMPLEMENTED INPUTS AVAILABLE 5 TWO TYPES OF TWO-LEVEL NETWORKS: and-or NETWORK SUM OF PRODUCTS (nand-nand NETWORK) or-and NETWORK PRODUCT OF SUMS (nor-nor NETWORK) x x 2 x 2 z x 0 z x x 0 (a) (b) Figure 5.2: and-or and or-and NETWORKS. E(,, ) = x 2x x 0 E(,, ) = (x 2 )( x 0)( x )

6 MINIMAL TWO-LEVEL NETWORKS 6. INPUTS: UNCOMPLEMENTED AND COMPLEMENTED 2. FANIN UNLIMITED 3. SINGLE-OUTPUT NETWORKS 4. MINIMAL NETWORK: MINIMUM NUMBER OF GATES WITH MINIMUM NUMBER OF INPUTS (minimal expression: min. number of terms with min. number of literals)

7 NETWORKS WITH DIFFERENT COST 7 x x 0 x2 x 2 z x 0 z Network A Network B Figure 5.3: NETWORKS WITH DIFFERENT COST TO IMPLEMENT f(,, ) =one-set(3,6,7).

8 MINIMAL EXPRESSIONS 8 EQUIVALENT BUT DIFFERENT COST E (,, ) = x 2 x 0 x E 2 (,, ) = x 2 x 0 x 2x x BOTH MINIMAL SP AND PS MUST BE OBTAINED AND COMPARED BASIS: ab ab = a (for sum of products) (a b)(a b ) = a (for product of sums)

9 9 GRAPHICAL REPRESENTATION OF SWITCHING FUNCTIONS: karnaugh MAPS 2-DIMENSIONAL ARRAY OF CELLS n VARIABLES 2 n CELLS cell i ASSIGNMENT i ADJACENCY CONDITION ANY SET OF 2 r ADJACENT ROWS (COLUMNS): ASSIGNMENTS DIFFER IN r VARIABLES REPRESENTING SWITCHING FUNCTIONS REPRESENTING SWITCHING EXPRESSIONS GRAPHICAL AID IN SIMPLIFYING EXPRESSIONS

10 x 0 x (a) (b) (c) (d) Figure 5.4: K-Maps

11 x 4 = 0 x 4 = Figure 5.5: K-map FOR FIVE VARIABLES

12 REPRESENTATION OF SWITCHING FUNCTIONS 2 f(,, ) = one-set(0,2,6) f(,,, ) = zero-set(,3,4,6,0,,3) f(,, ) = [one-set(0,4,5), dc-set(2,3)] 0 0 0

13 RECTANGLES OF -CELLS AND SUM OF PRODUCTS 3. MINTERM m j CORRESPONDS TO -CELL WITH LABEL j. 2. PRODUCT TERM OF n LITERALS RECTANGLE OF TWO AD- JACENT -CELLS x = x ( x 2) = x x 2x = m 3 m x 3 x Figure 5.6

14 RECTANGLES OF -CELLS AND SUM OF PRODUCTS (cont.) 4 3. PRODUCT TERM OF n 2 LITERALS RECTANGLE OF FOUR ADJACENT -CELLS = ( x )( x 2) = x 2x x 2 x = m 9 m m 3 m x 3 Figure PRODUCT TERM OF n s LITERALS RECTANGLE OF 2 s ADJACENT -CELLS

15 5 2 b xn... x x k... k 2 a Product of n (a + b) variables Figure 5.7: Representation of product of n (a + b) variables. x 0 x 3 x 2x 0 Figure 5.8: Product terms and rectangles of -cells. x 3 x 0 x 2 x 3

16 SUM OF PRODUCTS 6 represented in a K-map by the union of rectangles E(,,, ) = x 3 x 2 x E(a, b, c) = ab ac b c a c b

17 RECTANGLES OF 0-CELLS AND PRODUCT OF SUMS 7 0-cell 3 CORRESPONDS TO THE MAXTERM M 3 = x 3 x 2 x 0 RECTANGLE OF 2 a 2 b 0-cells SUM TERM OF n (a + b) LITERALS

18 MINIMIZATION OF SUMS OF PRODUCTS 8 IMPLICANT: PRODUCT TERM FOR WHICH f= A D x 2 B C Figure 5.9: Implicant representation. IMPLICANTS: x 3x 2x, ALL PRODUCT TERMS WITH PRIME implicant: IMPLICANT NOT COVERED BY ANOTHER IMPLICANT PRIME IMPLICANTS: x 2x,

19 FIND ALL PIs 9 a) f(,, ) = one-set(2,4,6) PIs: x 0 and x 0 b) f(,, ) = one-set(0,,5,7) PIs: x 2x,, and x x

20 20 c) f(,,, ) = one-set(0,3,5,7,,2,3,5) PIs:,, x, and x 3x 2x x 0

21 MINIMAL SUM OF PRODUCTS CONSISTS OF PRIME IMPLICANTS 2 q 0 0 p p 0 p 2 Figure 5.0: MINIMAL SUM OF PRODUCTS AND PRIME IMPLICANTS.

22 Example E(,, ) = x x 0 x 0 x 0 x x x x x 0 2 x 0 x x 0 not PIs: x x 0 and x 0 PI: x 0, x 0 REDUCED SP: E(,, ) = x 0 x 0

23 ESSENTIAL PRIME IMPLICANTS (EPI) 23 p e (a) = and p(a) = 0 FOR ANY OTHER PI p EPIs: x x 0 and NON-ESSENTIAL:, x 0. ALL EPIs ARE INCLUDED IN A MINIMAL SP

24 PROCEDURE FOR FINDING MIN SP 24. DETERMINE ALL PIs 2. OBTAIN THE EPIs 3. IF NOT ALL -CELLS COVERED, CHOOSE A COVER FROM THE RE- MAINING PIs

25 EXAMPLE FIND A MINIMAL SP: a) E(,,, ) = x 3x 2 x 3 PIs: x 3x 2, x 3, and ALL EPIs UNIQUE MIN SP: x 3x 2 x 3

26 26 b) E(,, ) = m(0, 3, 4, 6, 7) PIs: x x 0,, x 0, and EPIs: x x 0 and EXTRA COVER: x 0 or TWO MIN SPs: x x 0 x 0 and x x 0

27 27 c) E(,, ) = m(0,, 2, 5, 6, 7) PIs: x 2x, x 2x 0,,, x, and x 0 No EPIs TWO MIN SPs x 2x x 0 and x 2x 0 x

28 MINIMAL SPs FOR INCOMPLETELY SPECIFIED FUNCTIONS A minimal SP E(,,, ) = x 0 x 3 x 3x 2x

29 MINIMIZATION OF PRODUCTS OF SUMS 29 IMPLICATE: SUM TERM FOR WHICH f = 0. PRIME IMPLICATE: IMPLICATE NOT COVERED BY ANOTHER IM- PLICATE ESSENTIAL PRIME IMPLICATE: AT LEAST ONE CELL NOT IN- CLUDED IN OTHER IMPLICATE f(,,, ) = zero-set(7,3,5) THE PRIME IMPLICATES: (x 3 x 2 x 0) and (x 2 x x 0) BOTH ESSENTIAL

30 PROCEDURE FOR FINDING MIN PS 30. DETERMINE ALL PRIME IMPLICATES 2. DETERMINE THE ESSENTIAL PRIME IMPLICATES 3. FROM SET OF NONESSENTIAL PRIME IMPLICATES, SELECT COVER OF REMAINING 0-CELLS THE PRIME IMPLICATES: (x 0 x 2) and ( x ) BOTH ESSENTIAL, THE MINIMAL PS IS (x 0 x 2)( x )

31 MINIMAL TWO-LEVEL GATE NETWORK DESIGN: EXAMPLE Input: x {0,, 2,..., 9}, coded in BCD as x = (,,, ), x i {0, } Output: z {0, } Function: z = if x {0, 2, 3, 5, 8} 0 otherwise THE VALUES {0,,2,3,4,5} ARE DON T CARES x 3 0 MIN SP: z = x 2 x 2x 0 x MIN PS: z = (x 2 x )(x 2 )( x 0)

32 32 x x 2 x 2 z x 2 x 0 Figure 5.: MINIMAL and-or NETWORK

33 EXAMPLE THE K-MAP: Input: x {0,, 2,..., 5} represented in binary code by x = (,,, ) Output: z {0, } Function: z = if x {0,, 3, 5, 7,, 2, 3, 4} 0 otherwise min SP: z = x 3 x 3x 2x x x 0 x 2 min PS: z = (x 3 )( x 2 )( x )(x 3 x 2 x x 0) COST(PS) < COST(SP)

34 34 x 3 x 2 x z x 3 x 2 x x 0 Figure 5.2: MINIMAL or-and NETWORK

35 DESIGN OF MULTIPLE-OUTPUT TWO-LEVEL GATE NETWORKS 35 SEPARATE NETWORK FOR EACH OUTPUT: NO SHARING EXAMPLE 5.6 Inputs: (,, ), x i {0, } Output: z {0,, 2, 3} Function: z = 2 i=0 x i. THE SWITCHING FUNCTIONS IN TABULAR FORM ARE z z

36 EXAMPLE 5.6 (cont.) THE CORRESPONDING K-MAPS ARE z z MINIMAL SPs: z = z 0 = x 2x x 2 x 0 x x 0 4. MINIMAL PSs: z = ( )( )( ) z 0 = ( )( x x 0) (x 2 x 0)(x 2 x ) 5. SP AND PS EXPRESSIONS HAVE THE SAME COST

37 37 x x 2 x 2 z x x 0 z 0 x 0 Figure 5.3: MINIMAL TWO-OUTPUT and-or NETWORK

38 TWO-LEVEL NAND-NAND AND NOR-NOR NETWORKS 38 p, p 2,... ARE PRODUCT TERMS E = p p 2 p 3... p n E = (p p 2 p 3... p n) or E = NAND(NAND, NAND 2, NAND 3,..., NAND n )

39 39 x 7 x 7 x 6 x 6 x 5 x 4 z x 5 x 4 z (a) (b) Figure 5.5: TRANSFORMATION OF and-or NETWORK INTO nand NETWORK

40 EXAMPLE: NOR NETWORK 40 z = x 5(x 4 x 3)( ) x 5 x 5 x 4 z x 4 z x 3 x 3 (a) (b) Figure 5.6: EQUIVALENT or-and AND nor NETWORKS

41 LIMITATIONS OF TWO-LEVEL NETWORKS 4. THE REQUIREMENT OF UNCOMPLEMENTED AND COMPLEMENTED INPUTS IF NOT SATISFIED, AN ADDITIONAL LEVEL OF not GATES NEEDED 2. A TWO-LEVEL IMPLEMENTATION OF A FUNCTION MIGHT REQUIRE A LARGE NUMBER OF GATES AND IRREGULAR CONNECTIONS 3. EXISTING TECHNOLOGIES HAVE LIMITATIONS IN THE FAN-IN OF THE GATES 4. THE PROCEDURE ESSENTIALLY LIMITED TO THE SINGLE-OUTPUT CASE 5. THE COST CRITERION OF MINIMIZING THE NUMBER OF GATES IS NOT ADEQUATE FOR MANY msi/lsi/vlsi DESIGNS

42 PROGRAMMABLE modules: PLAs and PALs 42 STANDARD (FIXED) STRUCTURE CUSTOMIZED (PROGRAMMED) FOR A PARTICULAR FUNCTION DURING THE LAST STAGE OF FABRICATION WHEN INCORPORATED INTO A SYSTEM FLEXIBLE USE MORE EXPENSIVE AND SLOWER THAN FIXED-FUNCTION MODULES OTHER TYPES DISCUSSED IN Chapter 2

43 x n- AND Array Inputs Programmable array of AND gates Product terms -- programmable connection -- connection made (a) 2 3 r (b) k E z k- En Programmable array of OR gates Outputs OR Array 2 z z 0 E (enable) three-state buffers 43 Figure 5.7: PROGRAMMABLE LOGIC ARRAY (pla): a) BLOCK DIAGRAM; b) LOGIC DIAGRAM.

44 mos pla (or-and VERSION) 44 AND Array (NOR Array) Vdd Vdd a a b b c c Gnd Gnd Gnd Gnd Gnd pull-up devices (a + c) Gnd (b + c ) (a + b) Gnd pull-up devices OR Array (NOR Array) E c w = ((a + c) + (b + c ) ) = (a + b)(b + c ) z = ((a + b) + c ) = (a + b) c w z Figure 5.8: EXAMPLE OF pla IMPLEMENTATION AT THE CIRCUIT LEVEL: FRAGMENT OF A mos pla.

45 IMPLEMENTATION OF SWITCHING FUNCTIONS USING plas 45 A BCD-to-Gray CONVERTER Inputs: d = (d 3, d 2, d, d 0 ), d j {0, } Outputs: g = (g 3, g 2, g, g 0 ), g j {0, } Function: i d 3 d 2 d d 0 g 3 g 2 g g EXPRESSIONS: g 3 = d 3 g 2 = d 3 d 2 g = d 2d d 2 d g 0 = d d 0 d d 0

46 46 d 3 d 2 d d 0 OR Array AND Array -- programmable connection -- connection made g 3 g 2 g g 0 Note: a PLA chip would have more rows and columns then shown here Figure 5.9: PLA IMPLEMENTATION OF BCD-Gray CODE CONVERTER.

47 PAL : A PROGRAMMABLE MODULE WITH FIXED or ARRAY 47 FASTER, MORE INPUTS AND PRODUCT TERMS COMPARED TO PLAs x n- 2 E (enable) z z k z k- r three-state buffers AND Array -- programmable connection -- connection made Figure 5.20: LOGIC DIAGRAM OF A PAL

48 I I2 I3 I4 I5 I6 I7 I8 I O IO2 IO3 IO4 IO5 IO6 IO7 O8 I0 48 Figure 5.2: 6-INPUT, 8-OUTPUT pal(p6h8)