CS2504, Spring'2007 Dimitris Nikolopoulos. Boolean Algebra
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1 Boolean Algebra Truth tables can be expensive to store Represent truth tables with an equation Three operators A + B (OR, returns 1 if A or B is 1) A B (AND, returns 1 if A and B is 1) Ā (NOT, inverts A) Sufficient to implement any logic function 4
2 Boolean algebra laws CS2504, Spring'2007 Identity law: A + 0 = A, A 1 = A Zero and one laws: A + 1 = 1, A 0 = 0 Inverse laws: A + Ā = 1, A Ā = 0 Commutative laws: A+B=B+A, A B=B A Associative laws: A+(B+C)=(A+B)+C, A (B C)=(A B) C Distributive laws: A (B+C)=(A B)+(A C), A+(B C)=(A+B) (A+C) 5
3 Boolean Algebra CS2504, Spring'2007 Inputs Outputs A B C D E F F =A B C E= A B C A B C A B C D= ABC 6
4 Gates AND OR NOT AB AB 7
5 Decoders n inputs, 2 n outputs, output set bits which corresponds to binary value of input CS2504, Spring'2007 Inputs Outputs Out7 Out6 Out5 Out4 Out3 Out2 Out1 Out
6 Selectors (multiplexers) CS2504, Spring'2007 C= A SB S, log 2 n bits 9
7 Building a n-input multiplexer CS2504, Spring'2007 Selector built with a decoder E.g. input=010, output= Decoder output feeds n AND gates One AND gate has input 1 from decoder Large OR gate receives output of AND gates 10
8 Two-level logic Any logic function can be written in a canonical form: Every input is a true or complement variable Two levels of gates, one AND, the other OR Final output possibly inverted Representations: Sum of products (ORs of ANDs) Product of sums (ANDs of Ors) E= A B C A B C A B C 11
9 Two-level logic Production from truth tables: Each input which produces a 1 is a product Product consists of NOTs for the zero inputs and true for the 1 inputs Combinations that produce 1 are summed (Ored) Sum of products implemented with gates: A layer of AND gates for products A layer of OR gates for the sum Implemented with PLAs PLAs can implement any logic function with multiple inputs and outputs Cost depends on the function 12
10 Programmable Logic Array (PLA) CS2504, Spring'2007 n inputs, m outputs. Need (product terms with true output) AND gates hneed (number of true outputs of products) OR gates 13
11 Programmable Logic Array (PLA) CS2504, Spring'
12 Programmable logic arrays (PLAs) 15
13 Read-Only Memories (ROM) 2 m addressable entries (height of the ROM) m inputs Each entry n bits long (width of the ROM) Total capacity: 2 m x n ROM can encode any logic function directly from the truth table For each input burn the output in memory N functions with m inputs, need 2 m x n ROM ROMs implement full decodings of binary functions. PLAs implement partial decodings PLAs more economic for combinatorial logic ROMs easier to re-design for new functions than PLAs 16
14 Don't cares Assume the following logic function: 3 inputs: A, B, C 3 outputs: D, E, F D=1, if A or C is 1, regardless of B E=1, if A or B is 1, regardless C F=1, if exactly one input is 1, but we ignore it if D and E are true Don't cares: Ignored input or output combinations Marked with X in truth tables 17
15 Full Truth Table Inputs Outputs A B C D E F X X X X X 18
16 Reduced truth table Inputs Outputs A B C D E F X X 1 X X 1 1 X CS2504, Spring'2007 Don't cares enable a cheaper implementation of combinatorial logic. Karnaugh tables provide a representation for hand-optimization of combinatorial functions using don't cares. These days, this is a job of modern design tools. 19
17 Buses Collections of lines of signals. Example shows multiplexor selecting from a pair of 32-bit buses 20
18 Class test Parity functions CS2504, Spring'2007 A B C D
19 Logic design in action CS2504, Spring'2007 Let's design an almost complete MIPS ALU! 22
20 1-bit ALU Implementation of AND and OR instructions, assuming 1-bit arguments a and b 23
21 1-bit ALU Add adder with carry bit CarryOut= A B CarryIn A B CarryIn A B Inputs Outputs A B Carry-in Carry-out Sum
22 1-bit ALU Add adder with carry bit sum= A B CarryIn A BCarryIn A B CarryIn A B C Inputs Outputs A B Carry-in Carry-out Sum
23 1-bit adder's CarryOut signal CS2504, Spring'2007 Add adder with carry bit CarryOut= A B CarryIn A B CarryIn A B 26
24 1-bit ALU with AND, OR and adder 27
25 32-bit ALU with chaining CS2504, Spring'
26 1-bit ALU with AND, OR, ADD, SUB To support subtraction, we invert one of the inputs and add 1 (shows why two's complement representation is efficient) How do we add 1 to the inverted input? 29
27 1-bit ALU with AND, OR, NOR, ADD, SUB To support a NOR we observe that: AB= A B 30
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