JE SWITCHMODE Series NPN Silicon Power Transistor 1.5 AMPERES NPN SILICON POWER TRANSISTORS 300 AND 400 VOLTS 40 WATTS

Transcription

1 MJE33 SWITCHMODE Series NPN Silicon Power Transistor These devices are designed for highvoltage, highspeed power switching inductive circuits where fall time is critical. They are particularly suited for and V SWITCHMODE applications such as Switching Regulators, Inverters, Motor Controls, Solenoid/Relay drivers and Deflection circuits. Features Reverse Biased SOA with Inductive T C = C Inductive Switching Matrix. to. A, and C t A, C is 9 ns (Typ) 7 V Blocking Capability SOA and Switching Applications Information PbFree Package is Available* MAXIMUM RATINGS Rating Symbol Value Unit CollectorEmitter Voltage V CEO(sus)Î 4 Vdc CollectorEmitter Voltage V CEV Î 7 Emitter Base Voltage V EBO 9 Vdc Î Collector Current Continuous Peak (Note ). M Î 3 Adc Base Current Continuous Peak (Note ) ÎÎ I B.7 I BM. Adc Emitter Current Continuous ÎÎ I E. Peak (Note ) I EM Î Adc 4. Total Power T A = C Derate above C Î P D.4 Î. W mw/ C Total Power T C = C P D Î 4 W Derate above C 3 mw/ C ÎÎ Operating and Storage Junction T J, T stg 6 to Temperature Range + C THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Thermal Resistance, JunctiontoCase R JCÎ 3. C/W Thermal Resistance, JunctiontoAmbient R JA Î 89 C/W Maximum Load Temperature for Soldering Purposes: /8 from Case for Seconds T L Î 7 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Pulse Test: Pulse Width = ms, Duty Cycle %.. AMPERES NPN SILICON POWER TRANSISTORS 3 AND 4 VOLTS 4 WATTS 3 TO CASE 77 STYLE 3 MARKING DIAGRAM BASE COLLECTOR 3 EMITTER Y WW JE33 G YWW JE 33G = Year = Work Week = Device Code = PbFree Package ORDERING INFORMATION Device Package Shipping MJE33 TO Units/Box MJE33G TO (PbFree) Units/Box *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 6 January, 6 Rev. Publication Order Number: MJE33/D

2 MJE33 ELECTRICAL CHARACTERISTICS (T C = C unless otherwise noted) ÎÎ Characteristic ÎÎ Symbol ÎÎ Min Typ Max Unit OFF CHARACTERISTICS (Note ) ÎÎ CollectorEmitter Sustaining Voltage ( = ma, I B = ) ÎÎ V CEO(sus) 4 Î Vdc ÎÎ Collector Cutoff Current ÎÎ madc (V ÎÎ CEV = Rated Value, V BE(off) =. Vdc) (V CEV = Rated Value, V BE(off) =. Vdc, T C = C) Î Î ÎÎ Emitter Cutoff Current (V EB = 9 Vdc, ÎÎ = ) I EBO madc SECOND BREAKDOWN ÎÎ ÎÎ Second Breakdown Collector Current with bass forward biased EV I S/b RBSOA See Figure ÎÎ Clamped Inductive SOA with base reverse biased See Figure ON CHARACTERISTICS (Note ) ÎÎ DC Current Gain ÎÎ (I ÎÎ C =. Adc, V CE = Vdc) ( = Adc, V CE = Vdc) Î 8 Î 4 CollectorEmitter Saturation Voltage V CE(sat) ÎÎ Vdc ÎÎ ( =. Adc, I B =. Adc) Î Î. (I ÎÎ C = Adc, I B = Adc) ( =. Adc, I B =. Adc) Î Î 3 (I ÎÎ C = Adc, I B = Adc, T C = C) Î Î ÎÎ BaseEmitter Saturation Voltage ( =. Adc, I B ÎÎ V BE(sat) ÎÎ Vdc =. Adc) ÎÎ ( = Adc, I B = Adc) Î Î. ( = Adc, I B = Adc, T C = C). DYNAMIC CHARACTERISTICS ÎÎ ÎÎ ÎÎ ÎÎ CurrentGain Bandwidth Product ( = madc, V CE = Vdc, f = MHz) f T 4 Î MHz Output Capacitance (V CB = Vdc, I E =, f =. MHz) C ob pf SWITCHING CHARACTERISTICS Resistive Load (Table ) Delay Time t d.. s ÎÎ Rise Time Î (V CC = Vdc, = A, ÎÎ t r. Î s I Î B = I B = A, t p = s, ÎÎ Storage Time ÎÎ Duty Cycle %) t s Î 4 s ÎÎ Fall Time Î.4 Î.7 t f s Inductive Load, Clamped (Table, Figure 3) ÎÎ Storage Time ÎÎ t sv.7î 4 s (I Î C = A, V clamp = 3 Vdc, ÎÎ Crossover Time I B = A, V BE(off) = Vdc, T C ÎÎ t = C) c 9Î.7 s ÎÎ Fall Time ÎÎ t fi.î s. Pulse Test: PW = 3 s, Duty Cycle %. h FE

3 MJE33 h FE, DC CURRENT GAIN V, VOLTAGE (VOLTS), COLLECTOR CURRENT ( A) μ V CE = V V CE = V Figure. DC Current Gain C, CAPACITANCE (pf) V, VOLTAGE (VOLTS) V CE, COLLECTOREMITTER VOLTAGE (VOLTS) I B, BASE CURRENT (AMP) V CE = V T J = C T J = C C C T J = C Figure 3. BaseEmitter Voltage C C 7 C C C C C V /I B = 3 V V CE = V C REVERSE FORWARD V BE, BASEEMITTER VOLTAGE (VOLTS) =. A.3 A T J = C Figure. Collector Saturation Region /I B = 3 Figure 4. CollectorEmitter Saturation Region. C ib. A A. A C T J = C C V R, REVERSE VOLTAGE (VOLTS) T J = C C ob Figure. Collector Cutoff Region Figure 6. Capacitance 3

4 MJE33 Table. Test Conditions for Dynamic Performance REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING RESISTIVE SWITCHING TEST CIRCUITS V P W DUTY CYCLE % 68 t r, t f ns. F k N4933 NOTE. F 7 PW and V CC Adjusted for Desired R B Adjusted for Desired I B + Vk 33 N4933 k N4933 N 33 + V MJE R B I B T.U.T. N9 MJE 47 / W V BE(off) V CC L MR86* V clamp *SELECTED FOR kv. k V CE R B D 4. V TUT + V R C SCOPE CIRCUIT VALUES Coil Data: Ferroxcube Core #666 Full Bobbin (~ Turns) # GAP for 3 mh/ A L coil = mh V CC = V V clamp = 3 Vdc V CC = V R C = D = N8 or Equiv. R B = 47 TEST WAVEFORMS V CE (pk) TIME t V CE or V clamp t f t t f CLAMPED OUTPUT WAVEFORMS t t t Adjusted to Obtain t t L coil ( pk ) V CC L coil ( pk ) V clamp Test Equipment ScopeTektronics 47 or Equivalent +.3 V s 8. V t r, t f < ns Duty Cycle =.% R B and R C adjusted for desired I B and 4

5 MJE33 V CE IB 9% I B t sv PK 9% V clamp 9% t rv t fi t c V clamp % V clamp % PK t ti % Table. Typical Inductive Switching Performance AMP T C t sv t rv t fi CÎ s s s t ti s t c s. Î ÎÎ Î TIME Figure 7. Inductive Switching Measurements NOTE: All Data Recorded in the Inductive Switching Circuit in Table SWITCHING TIMES NOTE In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined. t sv = Voltage Storage Time, 9% I B to % V clamp t rv = Voltage Rise Time, 9% V clamp t fi = Current Fall Time, 9% t ti = Current Tail, % t c = Crossover Time, % V clamp to % An enlarged portion of the inductive switching waveforms is shown in Figure 7 to aid in the visual identity of these terms. For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN: P SWT = / V CC (t c )f In general, t rv + t fi t c. However, at lower test currents this relationship may not be valid. As is common with most switching transistors, resistive switching is specified at C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a SWITCHMODE transistor are the inductive switching speeds (t c and t sv ) which are guaranteed at C.

6 MJE33 RESISTIVE SWITCHING PERFORMANCE t, TIME ( s) μ V CC = V I.7 C /I B = t. r T J = C.3 t V BE(off) = V t, TIME ( s) μ 7 t V CC = V s /I B = T J = C t f Figure 8. TurnOn Time Figure 9. TurnOff Time r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D =.... SINGLE PULSE. Z JC(t) = r(t) R JC R JC = 3. C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t T J(pk) T C = P (pk) R JC (t) t, TIME OR PULSE WIDTH (ms) P (pk) t t DUTY CYCLE, D = t /t Figure. Thermal Response 6

7 MJE33 The Safe Operating Area figures shown in Figures and are specified ratings for these devices under the test conditions shown. IC, COLLECTOR CURRENT (AMP)..... T C = C dc. ms s THERMAL LIMIT (SINGLE PULSE) BONDING WIRE LIMIT SECOND BREAKDOWN LIMIT CURVES APPLY BELOW RATED V CEO s. ms MJE33 3 V CE, COLLECTOREMITTER VOLTAGE (VOLTS) Figure. Active Region Safe Operating Area SAFE OPERATING AREA INFORMATION FORWARD BIAS There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate V CE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure is based on T C = C; T J(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to % but must be derated when T C C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure may be found at any case temperature by using the appropriate curve on Figure 3. T J(pk) may be calculated from the data in Figure. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. IC, COLLECTOR CURRENT (AMP) T J C I B = A V 3 V V BE(off) = 9 V. V MJE V CEV, COLLECTOREMITTER CLAMP VOLTAGE (VOLTS) 8 REVERSE BIAS For inductive loads, high voltage and high current must be sustained simultaneously during turnoff, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias Safe Operating Area and represents the voltagecurrent conditions during reverse biased turnoff. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. Figure gives RBSOA characteristics. Figure. Reverse Bias Safe Operating Area POWER DERATING FACTOR THERMAL DERATING SECOND BREAKDOWN DERATING T C, CASE TEMPERATURE ( C) Figure 3. Forward Bias Power Derating 7

8 MJE33 PACKAGE DIMENSIONS TO CASE 779 ISSUE Z H Q B U 3 F A K V G S D PL M (.) M A M B M C J R (.) M A M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, 98.. CONTROLLING DIMENSION: INCH THRU 8 OBSOLETE, NEW STANDARD 779. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G.94 BSC.39 BSC H J K M TYP TYP Q R S U V.4. STYLE 3: PIN. BASE. COLLECTOR 3. EMITTER SWITCHMODE is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Phoenix, Arizona 883 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 8898 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguroku, Tokyo, Japan 3 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. MJE33/D