ENEL Digital Circuit Design Final Examination
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1 Department of Electrical and Computer Engineering ENEL Digital Circuit Design Final Examination April 26, 1999 Instructions: Please attempt all questions. Time allowed is 3 hours. The examination is closed-book. Calculators are permitted. The maximum number of marks is 100, as indicated. Please use a pen or heavy pencil to ensure legibility. 1
2 1 Positional Number Systems (15 marks) For questions (1.1)-(1.5) below, please show your work to receive full marks. 1.1 Convert to decimal. [3 marks.] 1.2 Convert to base 4. [3 marks.] 1.3 Convert to hexadecimal. [3 marks.] 1.4 Determine the radix r such that the following relationship is satisfied. [3 marks.] 31r = 5 r (1) 1.5 First convert to 8-bit two s-complement binary numbers and then calculate using two s-complement binary arithmetic. Express your answer as an 8-bit two s complement binary number. [3 marks.] 2 Switching Algebra (15 marks) 2.1 Simplify the following expression algebraically. [3 marks.] F = [x(xy) ][y(xy) ] (2) 2.2 Simplify the following expression algebraically. [3 marks.] F = wxy + wxyz + (w + w x z)(x z + w ) + wxy (3) 2.2 Manipulate the following expression in such a way that it can be implemented using only AND and exclusive-or operations. [3 marks.] F = AB CD + A BCD + AB C D + A BC D (4) 2.4 Express the following as a canonical sum and a canonical product. [3 marks.] F = A B + B C + A (5) 2.5 Express the complement of the following expression in POS form. [3 marks.] F = A,B,C,D(2, 3, 4, 5) (6) 2
3 3 Combinational Circuits (40 marks) 3.1 Using K-maps, obtain a minimal sum for the function F = w xz + xy + wyz + x y + wx (7) Carefully indicate the distinguished one-cells and the essential prime implicants. [5 marks.] 3.2 Design a combinational circuit that takes a 3-bit binary number ABC, where A is the MSB, and computes its two s-complement XY Z, where X is the MSB. Your circuit should be minimal in complexity and use only NOR gates and inverters. [9 marks.] 3.3 The logic symbol for a 74x151 8-to-one-line multiplexer is shown in Fig. 1. Fig. 1. A 74x151 multiplexer Implement the two s-complement converter in question (3.2) using multiplexers of this type. The MSB of the select lines is C. [6 marks.] 3.4 Design a combinational circuit that determines the square root of a number. The input is a four-bit positive binary-coded decimal (BCD) integer ABCD, where A is the MSB. The output is a 3-bit number with a 2-bit integer part XY, where X is the MSB, and a 1-bit fractional part Z. Thus, XY.Z is determined as the square root of ABCD. In the cases where the square root cannot be represented exactly, use the closest lower-valued estimate. Your circuit should be minimal in complexity and you have only NAND gates and inverters. You may assume that non-bcd values are never input to the circuit. [9 marks.] 3.5 A majority function is generated in a combinational circuit when the output is equal to 1 if the input variables have more 1s than 0s. The output is 0 otherwise. Design a four-input majority function circuit that is minimal in complexity and uses NAND gates and inverters. [6 marks.] 3
4 3.6 Draw a K-map and assign variables to the inputs of the AND-XOR circuit shown in Fig. 2 such that the output function is given by [5 marks.] F = W,X,Y,Z(6, 7, 12, 13) (8) Fig. 2. An AND-XOR circuit 4 Sequential Circuits (30 marks) 4.1 Analyze the clocked synchronous circuit given in Fig. 3. Write the excitation equations, the excitation/transition table, and the state/output table (use state names A-D for Q1Q2 = 00, 01, 10, 11). [6 marks.] Fig. 3. A clocked synchronous circuit for analysis 4.2 Design a clocked synchronous circuit based on D flip-flops that performs the function of a decade counter. Such a counter counts in binary counting sequence from 0 to 9 and then repeats. The circuit has one input x. When x = 0, the counter is disabled and the circuit remains in its current state; when x = 1, the counter is enabled and is allowed to count. The circuit s outputs are the state variables. Use the minimal cost approach for the unused states in your design. (... continued on next page...) 4
5 For your design, please provide the following: The state diagram. Show all transitions. The state/output table. The transition/excitation/output table. The minimized excitation equations. It is not necessary to draw the logic diagram for the circuit. [10 marks.] 4.3 Design a clocked synchronous circuit based on D flip-flops that detects a 2-bit Gray code sequence. The circuit has two inputs X and Y and a single Mealytype output Z. The system should begin in an initial state, and detect the Gray code sequence XY = 00, 01, 11, and 10. When the system receives the final XY = 11 in this sequence, the output Z should be set to 1, otherwise it is 0. If a value of XY is found to be out of sequence, the system is to return to the initial state awaiting a new sequence starting again with XY = 00. For your design, please provide the following: The state diagram. Show all transitions. The state/output table. The transition/excitation/output table. The minimized excitation equations. The minimized output equations. The logic circuit realization using DFFs, NAND gates, and inverters. [10 marks.] 4.4 The logic symbol for a positive-edge-triggered toggle flip-flop (TFF) is shown in Fig. 4. Fig. 4. A positive-edge-triggered TFF Write the characteristic equation for this TFF and show how to build one, first using a positive-edge-triggered DFF and then using a positive-edge-triggered JKFF. [4 marks.] Norm Bartley, April 26,
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