EGR 278 Digital Logic Lab File: N278L11A Lab # 11 Sequential Circuit Design using PLDs

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1 EGR 278 igital Logic Lab File: N278L Lab # Sequential ircuit esign using PLs. Objective The objective of this laboratory is to introduce the student to the use of sequential circuit design using Programmable Logic evices (PLs). Sequential circuits will be designed by the student using state equations and flip-flops and the circuits will be implemented and tested using a PL.. Materials readboard 5V Power Supply LL-07 Universal Programmer PLShell 5.0 Software GL22V Programmable Logic evice (PL) ommon-anode 7-segment display to-7-segment decoder/driver Seven 220 or 330 ohm resistors. Reference Handouts - PLShell Example: GL3.PS Loading PLShell 5.0 Instructions for using PLShell 5.0 PLShell 5.0 Manual GL22V ata Sheet Using the LL-07 Universal Programmer & Tester. Introduction Sequential circuit design considerations n important topic to consider when designing sequential circuits is the method to be used. There are several possible methods, including the excitation table method and design by state equations. nother important considerations is which type of flip-flop to use in the design: SR, JK,, or T. The JK flip-flop is the most versatile and typically yields the simplest circuit to implement. If a sequential circuit design is to be implemented using PLs where the number of gates required and the type of flip-flop to be used is not of great concern, it may be advantageous to simply use the simplest design method rather than the most efficient. The simplest design method is in many cases to use state equations with flip-flops. The general form of the state equation for a flipflop is: Q(t + 1) = So the input for each flip-flop is simply determined by finding an expression for the next state for that flip-flop. n example using this method is shown on the following pages. Furthermore, the example has been implemented using PLShell 5.0 and is shown in the handout to be provided by the instructor entitled GL3.PS.

2 Page 2 Example: esign a 4-bit counter using flip-flops. 4-bit counter, also called a modulo-16 counter, counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,,, 12, 13, 14, 15 and repeats. The state diagram is shown in Figure 1 below Figure 1: State diagram for a 4-bit counter The corresponding state table is shown in Figure 2 below. Note that the state is shown in decimal form in the state diagram, whereas it is shown in binary form in the state table with bit as the MS. Present State Next State Figure 2: State table for a 4-bit counter

3 Page 3 The characteristic equation for a flip-flop is very simple: Q(t + 1) =. So the expression for the next state is simply connected to the input on the flip-flop. Expressions for the next state for each of the four flip-flops is determined using Karnaugh maps shown in Figure 3 below. (t + 1) (t + 1) (t + 1) (t + 1) Figure 3: Karnaugh maps for the state equations for the 4-bit counter Minimal SOP expressions for each output yield the state equations shown below in Figure 4: (t + 1) = (t + 1) = + + (t + 1) = + (t + 1) = Figure 4: State equations for the 4-bit counter The state equations above are implemented in the circuit shown below in Figure 5. (t + 1) Q Q (MS) (t + 1) Q (t + 1) Q Q ount () Q (t + 1) Q lock Q Figure 5: Logic iagram for the 4-bit counter

4 Page 4 Implementing the 4-bit counter using PLShell The logic diagram in Figure 5 requires 16 gates or flip-flops. It can be easily implemented using a single PL. The state equations in Figure 4 can be rewritten in the appropriate format for PLShell. lso note that each term is Ned with LR, and active-high clear signal. The counter will be cleared to 0000 when LR is LOW and the counter will count normally when LR is HIGH. The state equations for the 4-bit counter as shown previously in Figure 4 are repeated below in order to compare them to the form of the state equations used in PLShell as shown in Figure 6 below. (t + 1) = (t + 1) = + + (t + 1) = + (t + 1) = Figure 4: State equations for the 4-bit counter (shown for a second time) Q := LR (Q / Q + Q / Q + Q / Q + /Q Q Q Q) Q := LR (Q / Q + Q / Q + /Q Q Q) Q := LR (Q / Q + /Q Q) Q := LR / Q Figure 6: State equations for the 4-bit counter in PLShell format

5 Page 5 E. Preliminary Work 1. Each student (no teams) should design a counter that will count out each of the unique digits of his or her SSN in the order in which they occur, followed by the all digits from 0 to 9 that do not occur in the SSN from highest to lowest. Note that all counting sequences will have all ten digits. In order to make the counter "self-starting", let all unused counts ( - 15) go to the first count in your sequence. n example is shown below. Example: SSN = ounting sequence = 1, 4, 8, 6, 3, 9, 7, 5, 2, 0 digits in your digits from 0 to 9 SSN in the that are not in order in which your SSN from they occur highest to lowest Your design should include the following: a state diagram (be sure to include all 16 counts) a state table the K-maps used to generate the state equations the state equations the.ps file used to implement the counter using PLShell 5.0 using an GL22V PL. The PS file should be well documented. Include a SIMULTION section that initiates the counter to count 0 and cycles the counter through 2 full cycles (20 counts) ) and also tests the LR signal for resetting the counter. the corresponding.rpt file the corresponding.hst file (waveform file) with a vector OUNT displaying the count and showing proper operation of the clear signal for resetting the counter the corresponding JEE file (.JE) on a floppy disk ready to download into the PL programmer at the beginning of the lab. You do not need to print this file. 2. If the counter were to be implemented using flip-flops, 2-input N gates, 2-input OR gates, and INVERTERS, draw the logic diagram. Include the input clock. Label the output count. What is the total number of gates required? Note that only one PL will be used to replace this circuit. 3. Generate complete circuit documentation for the counter to be implemented. The documentation should include the connection of the 4 outputs on the PL to a 7-segment display via a to-7-segment decoder/driver and the input clock connection from a 1 Hz clock signal produced by either a 555 timer or the Leader 1300 signal generator. If a 555 timer is used, show the calculations used to determine the resistor and capacitor values. 555 Timer (1 Hz clock) GL22V PL to-7 sement decoder/driver

6 Page 6 F. Laboratory Work Program the PL using the JE file generated in the Preliminary Work. onstruct the circuit used to test the PL according to the wire-list generated in step 3 of the Preliminary Work. Use a 1 Hz clock generator to clock the circuit (using either a 555 timer or the Leader 1300 signal generator). The output should count through the appropriate sequence and be displayed on the 7- segment display. emonstrate the circuit to the instructor.