LABORATORY MODULE. EKT 121/4 Digital Electronics I

Transcription

1 LABORATORY MODULE EKT 121/4 Digital Electronics I Mohd. Najmuddin Mohd. Hassan Zahereel Ishwar Abdul Khalib Mohammad Nazri Md. Noor Rafikha Aliana A.Raof School of Computer & Communications Engineering Universiti Malaysia Perlis

2 - FOR UniMAP INTERNAL CIRCULATION ONLY- EKT 121/4 Digital Electronics I Printed in , Universiti Malaysia Perlis All rights reserved. No part of this book may be reproduced or transmitted in any form by any means, electronic, mechanical, or otherwise, whether now or hereafter devised, including photocopying, recording, or by any information storage and retrieval system without express written prior permission from the publishers. Published by : Unit Penerbitan, Perpustakaan, Universiti Malaysia Perlis Tingkat 1, Bangunan KWSP, Jalan Bukit Lagi, Kangar, Perlis. Tel : , Fax : penerbitan@unimap.edu.my

3 CONTENTS PREFACE EXPERIMENT 1 : LOGIC GATES 1 ~ 8 EXPERIMENT 2 : BOOLEAN THEOREMS 9 ~ 18 EXPERIMENT 3 : DECODERS 19 ~ 24 EXPERIMENT 4 : MULTIPLEXER & DEMULTIPLEXER 25 ~ 30 EXPERIMENT 5 : FLIP-FLOP 31 ~ 38 EXPERIMENT 6 : SHIFT REGISTERS 39 ~ 44 EXPERIMENT 7 : COUNTERS 45 ~ 49 REFERENCES 50 APPENDIX LOGIC IC DATASHEETS a) 74LS00-2 input NAND Gate b) 74LS02-2 input NOR Gate c) 74LS04 - INVERTER Gate d) 74LS08-2 input AND Gate e) 74LS11-3 input AND Gate f) 74LS32-2 input OR Gate g) 74LS47 - BCD-to-7 segment Decoder h) 74LS48 - BCD-to-7 segment Decoder i) 74LS74 - D flip-flop j) 74LS76 - JK flip-flop k) 74LS90 - Decade Counter l) 74lS153-4-to-1 Multiplexer

4 PREFACE This laboratory module serves as a guidance and practical book for students who are registered for the EKT 121/4 Digital Electronics I subject. It is designed to allow the students grasp the theoretical concepts imparted during the lecture sessions and apply them into their practical purposes. The contents of this module will be used by UniMAP students for laboratory practices in the goal to help them further understand the subject in a more effective manner. There are seven (7) experiments on this subject that need to be performed by the students. It will involve a lot of techniques obtained during the lecture sessions in order to fulfill the major part of the lab sessions and will also cover the students knowledge and skills with the use of logic integrated circuits (ICs), datasheets and deep understanding of circuit troubleshooting and component and equipment man-handling. It is hoped that the students would enjoy every part of the laboratory works and thus, would increase their understanding on the fundamentals of digital designs.

5 LAB 1: LOGIC GATES OBJECTIVES 1. To verify the operation of OR, AND and NOT gates. 2. To construct a simple combinational logic circuits. EQUIPMENT/COMPONENTS A DC power supply capable of 5V DC output An oscilloscope A multimeter Logic Gate IC : 7404 (1pc), 7432 (1pc), 7408 (2pc) Light Emitting Diode (4pc) Resistors : 330Ω (4pc) Switches (3pc) INTRODUCTION Digital circuits are often referred to as switching circuits because their control devices (e.g. diodes and transistors) are switched between the two extremes of ON and OFF. Logic gates have one or more inputs with one output. They respond to various input combinations. A truth table shows this relationship between circuits s input combinations and its output. To determine the total number of different combinational to be listed in the truth table, use the equation: Number of Combinations = 2 N where, N = number of inputs The truth table for a particular circuit explains how the circuit behaves under normal condition. In this experiment, three logic gates are covered: the OR, AND and NOT gates. You should recall that the logic levels, 0 and 1, have voltage assignments. For TTL circuits, a logic 0 can be anywhere from 0V to +0.8V, and a logic 1 is in the range of +2.0 V to +5.0V. PROCEDURE 1. The NOT Gate: Figure 2.1 shows the logic symbol of NOT gate. The NOT gate is also known as an inverter. Figure 2.1: NOT Gate Logic Diagram 1

6 2. Refer to the data sheet for the 7404 IC. It contains six NOT gates. Wire one of them as follows: Note: V cc = +5V to pin 14; GND to pin 7. Figure Construct a truth table for a NOT gate at Table 2.1, then verify the NOT operation by completing the truth table. (Please fill Table 2.1 at the results) 4. The OR Gate: Figure 2.3 shows the logic symbol of OR gate. Figure 2.3: OR Gate Logic Diagram 5. Refer to the data sheet for the 7432 IC. It contains four OR gates. Wire one of them as follows: Note: Vcc = +5V to pin 14; GND to pin 7. Figure You will now verify the OR operation by completing the truth table in Table 2.2. (Please fill Table 2.2 at the results) 2

7 7. The AND Gate: Figure 2.5 shows the logic symbol of AND gate. Figure 2.5: AND Gate Logic Diagram 8. Refer to the data sheet for the 7408 IC. It contains four AND gates. Wire one of them as follows: Figure 2.6 Note: Vcc = +5V to pin 14; GND to pin You will now verify the AND operation by completing the truth table in Table 2.3. (Please fill Table 2.3 at the results) RESULTS Input Output LED (on / off) Level ( 1 / 0 ) Table 2.1: Truth table of NOT gate Input Output A B LED (on / off) Level ( 1 / 0 ) Table 2.2: Truth table of OR gate 3

8 Input Output A B LED (on / off) Level ( 1 / 0 ) Table 2.3: Truth table of AND gate ACTIVITY SHEET PART A 1. Construct the combinational circuit shown in Figure 2.7: Figure 2.7 : Combinational Circuit 2. Assign your inputs A, B and C with switches that are connected to +5VCC and GROUND respectively. Take note to determine where your MSB to LSB values are located i.e; ABC or CBA. Enter your input name following this rule. 3. Assign your outputs W, X, Y and Z with your light emitting diodes (LEDs). 4. Record all your output level for all input states into Table 2.4. LED ON = 1 INPUTS OUTPUT LED (on=1 / off=0) W X Y Z Table 2.4: Circuit Operation 4

9 PART B Given to you is a Boolean Expression : X = ( A + B ).( B + A ) 1. What kind of operations does the symbols + and. means? 2. Simplify this expression to get the logic equation. 3. Construct your combinational circuit of this logic expression using the components supplied. 4. Create a Truth Table in Table 2.5 for this operation and record your values for each state. INPUTS OUTPUT REPORT REQUIREMENT The lab report should include the following: Table 2.5 : Truth Table of Boolean Expression 1. Summary of each experiment done. 2. Results of each experiment. 3. Discussions on each operations of the gates. 4. For Activity Part B, describe the kind of equation given, the simplified Boolean equation, include the circuit diagram and the truth table. 5. Remarks on any possible failures and measures done to overcome this problem. 6. Conclusion for the experiments. 5

10 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME : METRIC NO.: COURSE : LAB EXPERIMENT : Input Output A LED (on / off) Level ( 1 / 0 ) Instructor Signature Table 2.1: Truth table of NOT gate Input Output A B LED (on / off) Level ( 1 / 0 ) Instructor Signature Table 2.2: Truth table of OR gate Input Output A B LED (on / off) Level ( 1 / 0 ) Instructor Signature Table 2.3: Truth table of AND gate 6

11 INPUTS OUTPUT LED (on=1 / off=0) W X Y Z Table 2.4: Circuit Operation Instructor Signature INPUTS OUTPUT Instructor Signature Table 2.5 : Truth Table of Boolean Expression 7

12 LAB 2: BOOLEAN THEOREMS OBJECTIVES 1. To implement DeMorgan's theorems in circuit simplification. 2. To design a combinational logic circuit with simplest logic gates representation using Karnaugh Mapping Technique. EQUIPMENTS/COMPONENTS A DC power supply capable of 5V DC output A multimeter Logic Gate IC : 7400(1pc), 7402(1pc), 7404 (1pc), 7432 (1pc), 7408 (1pc) Light Emitting Diode (2pc) Resistors : 330Ω (2pc) Switches (4pc) INTRODUCTION Theorems of Boolean Algebra are a set of rules used with digital variables and logical operations to develop, manipulate and simplify logical expressions. Boolean Algebra provide systematic means for discovering alternative expressions. This lab session will let you get familiarize with De Morgan s and Karnaugh Technique. De Morgan Theorems De Morgan's theorem allows large bars in a Boolean expression to be broken up into smaller bars over individual variables. De Morgan's theorem says that a large bar over several variables can be broken between the variables if the sign between the variables is changed. From the above equation, it is clear that a NAND gate is equal to an OR gate with inverted inputs and a NOR gate is equal to an AND gate with inverted inputs. In order to reduce expressions with large bars, the bars must first be broken up. This means that in some cases, the first step in reducing an expression is to use De Morgan's theorem. De Morgan's theorem is useful in the implementation of the basic gate operations using alternative gates, particularly operations involving NAND and NOR gates. For this session, you will implement De Morgan Theorem into a given Boolean Equation. Karnaugh Maps Karnaugh Map provides a systematic method for simplifying Boolean expressions. Using K-Map is very similar to truth table. K-Map can be used for expressions with two, three, four or five variables. 8

13 Number of cells in a K-Map is equivalent to the number of possible input variable combinations (2 n ). As an example: For 3-variables; number of cells are 2 3 = 8 The cells in K-Map are arranged so that only one single variable changes between adjacent cells. In the experiment, you will be given a design problem. You should be able to interpret the design problem into a truth table and apply the Karnaugh Map technique to find the simplest logic expression. Finally, you have to construct and test the circuit. PROCEDURE PART A : Simplification using De Morgan's theorems 1. Draw a logic diagram for the equation : Y = AB B+C 9

14 2. Construct the circuit using the diagram you drew in Step 1. Connect toggle switches to inputs A, B and a LED to the circuit output, Y. Set the toggle switches to each input combination listed in Table 2.1, and record the output value observed in the table. INPUTS OUTPUT Table 2.1 : Step 1 Circuit Operation 3. Apply De Morgan s laws to remove the top inversion bar by changing the sign. Get the simplified expression and draw the logic circuit diagram in the space given below: 10

15 4. Construct a logic circuit for the simplified expression obtained in step 3 and again complete the truth table in Table 2.2. INPUTS OUTPUT Table 2.2 : Step 3 Circuit Operation 5. Write your observation based on the results. 11

16 PART B: Design Problem using Karnaugh Mapping Technique A jet aircraft employs a system for monitoring the rpm, pressure, and temperature values of its engines using sensors that operate as follows: RPM sensor output = 0, only when speed < 4800 rpm P sensor output = 0, when pressure <220 psi T sensor output = 0, only when temperature < 200 F Figure 2.1 shows the logic circuit that controls a cockpit warning light for certain combinations of engine conditions. Assume that a HIGH at output W activates the warning light: (a) Create your truth Table with appropriate input-output combinations (b) Determine what engine conditions will give warning to the pilot. (c) Using K-Map technique to obtain your simplified Boolean equation. (d) Change this circuit to one using all NAND gates and constructs the circuit. Figure 2.1 REPORT REQUIREMENT The lab report should include the following: 1. Summary of each experiment done. 2. Results of each experiment. 3. Discussions on each operation of the gates. 4. For Activity Part B, include your K-Map table, the simplified Boolean equation, the circuit diagram, the truth table and the engine conditions. 5. Remarks on any possible failures and measures done to overcome this problem. 6. Conclusion for the experiments. 12

17 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME : METRIC NO.: COURSE : LAB EXPERIMENT : PART A : Simplification Using De Morgan Theorem equivalent operation Y = inputs outputs inputs outputs Table 2.1 : Step 1 Operation Table 2.2 : Step 3 Operation INSTRUCTOR S SIGNATURE: 13

18 PART B : Karnaugh Map Design Method (a) INPUTS OUTPUT Truth Table (b) The engine conditions that will give warning to the pilot: (c) K-Mapping : Simplified Boolean equation: 14

19 (d) Logic Circuit Diagram using all NAND gates INSTRUCTOR S SIGNATURE: 15

20 LAB 3: DECODERS OBJECTIVES 1. To expose the student with one of the combinational logic circuits application. 2. To understand the operation of decoder. 3. To design and construct a type of decoder. EQUIPMENTS/COMPONENTS DC power supply capable of 5V DC output Pattern generator Multimeter Logic Gate ICs : 7404 (1pc), 7432 (2pc), 7448 (1pc), 7490 (1pc) Seven Segment Display (1pc) Resistors : 330Ω (1pc) Switches (4pc) INTRODUCTION A decoder is a circuit that creates an output based on the binary states of a given input. It is used in many applications. One example is in computers for input/output selection. Computers must communicate with a variety of external devices (e.g. printers, disk drives, modem etc.) by sending and/or receiving data through what is known as input/output ports. In this case, a decoder is used to select the I/O port as determined by the computer so that data can be sent or received from a specific external device. Other than that, systems such as digital watches, calculators and cellular phones use decoders for multisegment display. In this case, decoders are needed in these systems to decode the binary data into the multi-segment data to drive the display. In this session, you will first create a normal BCD counter using a BCD-to-seven segment display and its decoder by using existing logic ICs. The display should show the following : The second part will enhance your decoding system and let you study further the addition of other decoding ICs into your construction. 16

21 PROCEDURE Part A In this lab you will experiment with a decoder and associated hardware to derive a BCD counter onto a seven-segment LED display. Your job for this lab is to design and test a circuit to convert a 4-bit BCD signal into a 7-bit control signal according to the following figure: Figure 3.1 : BCD counter schematic diagram 1. Construct the circuit in Figure 3.1 onto your breadboard. From the output of your 7448 BCD-to-7 segment decode, wire the pins to the 7 seven segment display as shown in Figure 3.2 below. Figure 3.2 : 7 Segment display schematic diagram 17

22 2. Study the light emitted on every value shown based from the decoder connector. Fill in the table 3.1. Part B Table 3.1 : The 7-segment output truth table 1. Instead of using the 7448 BCD decoder, create your own combinational logic decoder that will only display the following counting sequence. 2. Prepare the necessary steps using the K-map technique and obtain the Boolean equation. Take note to consider unwanted values as don t care states and redundant for any current values. 18

23 3. Construct your design onto the breadboard. Use the switches first as your inputs. Verify with your instructor on your design. 4. Replace your input switches with the 7490 decade counter IC. Verify the counting sequence with your instructor. Take note to remember where your inputs are. This is important when wiring between your two systems. 5. For your experiment data sheet, submit your Part B : (a) Truth table (b) K-Map (c) Schematic Design CAUTION!!! Marks will be deducted for messy submissions. REPORT REQUIREMENT The lab report should include the following: 1. Summary of each experiment done. 2. Results of each experiment. 3. Discussions on each operation. 4. For Part B, include your K-Map table, the simplified Boolean equation, include the circuit diagram and the truth table. 5. Remarks on any possible failures and measures done to overcome this problem. 6. Conclusion for the experiments. 19

24 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME : METRIC NO.: COURSE : LAB EXPERIMENT : Part A Table 3.1 : The 7-segment output truth table Circuit construction verification Instructor s signature : 20

25 Part B 1. Attach together with this experiment sheet are your Counting sequence truth table K-Map Schematic Design CAUTION!!! Marks will be deducted for messy submissions 2. Counting sequence using switches. Is the circuit construction OK? Instructor s signature : 3. Counting sequence using the 7490 decade counter. Is the circuit construction OK? Instructor s signature : 21

26 LAB 4: MULTIPLEXER & DEMULTIPLEXER OBJECTIVES 1. To understand the operation of a multiplexer and demultiplexer. 2. To design basic multiplexer. EQUIPMENTS/COMPONENTS DC power supply capable of 5V DC output Multimeter Logic ICs : 7404(2pc), 7408(3pc), 7411(2pc), 7432(1pc), 74153(3pc) Light Emitting Diode (6pc) Resistors : 330Ω (2pc) Switches (5pc) INTRODUCTION A digital multiplexer or data selector is a logic circuit that accepts several digital data inputs and selects one of them at any given time to pass on to the output. Primarily they are used for data routing which selects a transmission path for outgoing data according to the coding criteria established by binary inputs. The routing of the desired data input to the output is controlled by SELECT inputs (often referred to as ADDRESS inputs). Figure 4.1 shows the functional diagram of a general digital multiplexer. The inputs and output are drawn as wide arrows rather than lines; this indicates that they may actually be more than one signal line. Figure 4.1: Functional diagram of digital multiplexer (MUX) 22

27 A demultiplexer performs the reverse operations. It takes a single input and distributes it over several outputs based on the selector. Figure 4.2 shows the functional diagram for digital demultiplexer (DEMUX). The large arrows for inputs and outputs can represent one or more lines. The select inputs code determines to which output the DATA input will be transmitted. In other words, the demultiplexer takes one input data sources and selectively distributes it to 1 of N output channels just like a multiposition switch. Figure 4.2: Functional diagram of digital demultiplexer (DEMUX) For this lab session, you are required to first build your own multiplexing system which will include the combination of a 4:1 multiplexer (MUX) and a 1:5 demultiplexer (DEMUX). 23

28 PROCEDURE Part A: Designing a multiplexing system Construct your very own multiplexing system which has a 4-to-1 multiplexer (MUX) to transmit your data and received by a 1:5 demultiplexer (DEMUX). 1) Construct the truth table and get the Boolean expression for your MUX and DEMUX. 2) Draw the circuit diagram for a 4:1 MUX. 3) Draw the circuit diagram for a 1:5 DEMUX based on the given Ics. 4) Construct your MUX and DEMUX together based on the following diagram in Figure 5.3. Take note on the tasks below : a. Construct your MUX using the input AND gates. b. Construct your DeMUX using the input AND gates. You may need to redesign your schematic first to suit the above requirements due to limited components. 5) Assign the toggle switches as your S0, S1, S2, S3, and S4 selector. Figure 4.3: Multiplexing System Schematic 6) Change the connection of your D0 jumper wire from LO to HI. Set your S1 to HI and S0 to LO. Set your S4, S3 & S2 to LO. Fill in Table 5.1 upon your result. 24

29 7) Fill in the rest of the data given in Table ) Demonstrate to your instructor and get your instructor s signature for verification. Selector LED state (ON/OFF) D0 D1 D2 D3 S1 S0 F S4 S3 S2 L0 L1 L2 L3 L4 HI LO LO LO HI LO LO LO LO LO LO LO HI LO LO LO LO HI HI LO LO LO LO LO HI LO LO LO HI LO LO LO HI LO HI HI LO LO LO HI HI HI HI HI LO LO LO HI LO HI LO LO LO HI LO HI HI HI LO LO HI LO LO Table 4.1: Data Output of Multiplexing System Part B: Design Problem 1. Draw a block diagram of a 16:1 multiplexer using 4:1 multiplexers. 2. Construct your circuit onto the breadboard using the ICs provided. 3. Test your construct based on your block diagram. 4. Demonstrate to your instructor for verification. REPORT REQUIREMENT The lab report should include the following: 1. Summary of each experiment done. 2. Results of each experiment. 3. Discussions on each operation based on your results. 4. Include your Truth Tables, K-Maps, the simplified Boolean equations and circuit diagrams. 5. Remarks on any possible failures endured throughout your experiment and steps or measures you have done to overcome that problem. 6. Conclusion for the experiments. 25

30 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME: COURSE: METRIC NO.: TABLE NO.: EXPERIMENT TITLE: Part A 1. Attachments : 4:1 Multiplexer Truth Table 4:1 Multiplexer K-Map and Boolean equation 4:1 Multiplexer Circuit diagram 1:5 Demultiplexer Truth Table 1:5 Demultiplexer K-Map and Boolean equations 1:5 Demultiplexer Circuit diagram 2. Circuit Operation Selector LED state (ON/OFF) D0 D1 D2 D3 S1 S0 F S4 S3 S2 L0 L1 L2 L3 L4 HI LO LO LO HI LO LO LO LO LO LO LO HI LO LO LO LO HI HI LO LO LO LO LO HI LO LO LO HI LO LO LO HI LO HI HI LO LO LO HI HI HI HI HI LO LO LO HI LO HI LO LO LO HI LO HI HI HI LO LO HI LO LO Table 4.1: Data Output of Multiplexing System INSTRUCTOR S SIGNATURE CIRCUIT SETUP: CIRCUIT CONSTRUCT OPERATION CONFIRMED: 26

31 Part B 1. Boolean Expression: 2. Attachments: a) Schematic Diagram INSTRUCTOR S SIGNATURE CIRCUIT SETUP: CIRCUIT CONSTRUCT OPERATION CONFIRMED: 27

32 LAB 5: FLIP-FLOP OBJECTIVES 1. To construct the basic circuit of latches and flip-flops using basic gates. 2. To investigate the operation of latches and flip-flops. 3. To determine the input and output states of the circuits constructed. EQUIPMENTS/COMPONENTS DC power supply capable of 5V DC output Multimeter Pattern generator Logic ICs : 7402(1pc), 7408(1pc), 7476(1pc) Light Emitting Diode (4pc) Resistors : 330Ω (4pc) Switches (4pc) INTRODUCTION In the previous lab sessions, you have studied forms of combinational logic. This session will introduce the fundamentals of sequential logic. You will be introduced to two types of device which perform the basis of multivibratators such as bistable, monostable and astable and memory elements like registers. The two categories of device which are bistable are the latch and the flip-flop. A bistable device means that it has two stable states called SET and RESET; in which they can retain either of these states indefinitely, making bistable devices useful to be functioned as storage devices. The latch and flip-flop are basic elements that are able to store binary information. Even though they are made up of combinational logic gates that have no storage capability, the way they are connected permits information to be stored. Both have basic feedback design circuits but the differences between the latch and the flip-flop is how it can be triggered to change their outputs between the two states. This lab will introduce you the design to build your own latch and flip-flops. You will construct, examine and verify its operations individually. Finally you will determine the actual difference between the two fundamental devices. 28

33 PROCEDURE 1. R-S flip-flop: Construct a circuit as shown in Figure 5.1. Connect switches to the input and complete Table 5.1 by monitoring the output using the LED display. Figure Make a modification on the previous circuit by connecting the circuit as illustrated at Figure 5.2. Connect another switch for the CLK input and complete Table 5.2. Figure J-K flip-flop: Combine the circuit constructed in procedure 2 with gate AND as shown in Figure 5.3. Perform the following series of test on the circuit by completing Table 5.3. Figure 5.2 Figure

34 4. Figure 5.4 shows IC 7476 which is a JK flip-flop. Verify the operation of JK flipflop by ignoring the PRE and CLR input. Fill in the results at Table 5.4. Figure Experiment in procedure 4 is repeated but this time the PRE and CLR input are considered. Test all the possible input combination and complete Table T flip-flop: Apply the rectangular waveform at 1 KHz frequency to the CLK input of JK flip-flop. Set the input T at logic 1 as shown in Figure 5.5. Use oscilloscope with dual channel to display the output waveform for CLK and signal Q. Sketch the output Q waveform at Diagram 5.1. Figure

35 7. D flip-flop: Connect an inverter to the input K of flip-flop JK as illustrated in Figure 5.6 and complete Table 5.6. Figure 5.6 REPORT REQUIREMENT The lab report should include the following: 1. Summary of each experiment done. 2. Results of each experiment. 3. Discussions on each operation based on your results. 4. Include your remarks (if any) on any possible failures endured throughout your experiment and steps or measures you have done to overcome that problem. 5. Conclusion for the experiments. 31

36 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME: COURSE: MATRIC NO.: TABLE NO.: EXPERIMENT TITLE: Input Output R S Q Q Input Table 5.1 Table 5.2 Output R S CLK Q Q Signature: Signature: Input Output J K CLK Q Input Output J K CLK Q Table 5.3 Table 5.4 Signature: Signature: 32

37 Input Output CLR PRE J K CLK Q Table 5.5 Diagram 5.1 Signature: 33

38 Input Output R CLK Q Q Table 5.6 Signature: 1. Based on your observations, explain the different between RS flip-flop and JK flipflop in term of its operation. 2. Discuss the effect of PRE and CLR in JK flip-flop. 34

39 LAB 6: SHIFT REGISTERS OBJECTIVES 1. To explain the operation of a serial shift register. 2. To describe the function of shift register in ring counter. EQUIPMENT/COMPONENTS A DC power supply capable of 5V DC output A pattern generator for square wave signals A multimeter Logic Gate IC : 7474 (2pc) Light Emitting Diode (4pc) Resistors : 330Ω (4pc) Toggle Switches (2pc) INTRODUCTION An introduction to flip-flops in the previous session will now be extended into introducing many important sequential logic designs when they are combined together with combinational logic circuits. Among the most important sequential circuits that are widely used in digital systems are registers. A 1-bit register requires one flip-flop, so an array of these flip-flops are required to store binary information either in 1, 4, 8, 16 or 32 bits of data accordingly. Registers can both receive and transmit data either in serial (one-bit at a time) or in parallel (simultaneously) form. They can be classified depending upon the way in which data are entered and exited. There are four modes of operation : 1. serial in, serial out (SISO) 2. serial in, parallel out (SIPO) 3. parallel in, serial out (PISO) and 4. parallel in, parallel out (PIPO). A register designed to transfer any given data from one flip-flop to another commonly known as Shift Registers. The data bits are shifted in the flip-flops with the occurrence of clock pulses either in the right direction (right-shift registers) or in the left direction (leftshift register) before sending it back out again. A register that can shift data in both ways is called a bi-directional shift register. This lab session will give you a task to construct the given shift register circuits and verify the operations with your instructor. 35

40 PROCEDURE PART A : Shift Register Operation 1. Refer to the figure below and construct the circuit onto the breadboard. D Flipflops are used in this experiment. 1 Hz Figure 6.1 : D flip-flop Shift Register (Take note of the components assigned to the DATA INPUT, Clock, CLEAR / RESET pins and the output pins of each D flip-flop, Q A, Q B, Q C and Q D respectively). 2. Set your switch A to LO for initial stage and Switch B to HI. Switch B is to reset your circuit. If any LEDs are ON, reset your system by setting switch B to LO and then set it back to HI again. The reset mode for the D flip-flop requires an active low input pulse. 3. Assign your Clock input to the pattern generator that generates a square wave with a frequency of 1 Hz. Connect the waveform to your system. As explained earlier on, the shift register operation is based on a clock pulse from the square wave form. One clock pulse is defined as or depending to the mode of edge-triggered operation of the flip-flop. 4. Refer to Table 6.1. Set your initial Data Input value to HI at the first clock pulse. Record your output values. 5. Complete Table 6.1 by recording the output values based on the given input values. Demonstrate and verify your operation with your instructor. Caution : If your register is too fast to record, you can slow down the frequency to suit your pace. You may need to reset your system so that you can follow up on the input values you have missed. 36

41 Clock OUTPUT LED Switch A Pulse A B C D Initial Stage st 1 2 nd 1 3 rd 1 4 th 1 5 th 0 6 th 0 7 th 0 8 th 0 9 th 1 10 th 0 11 th 1 12 th 1 13 th 0 14 th 0 15 th 0 16 th 1 PART B : Ring Counter Operation Table 6.1 : Shift Register Operation 1. Reconstruct your existing shift registers into a Ring Counter. Switch A will then be connected to the PRESET (PR) at pin 4 of your first D Flip-flop as your DATA INPUT. Refer Figure 6.2 : 1 Hz Figure 6.2 : Ring Counter Schematic 2. Set your Switch A to LO and Switch B to HI. Reset your system if necessary by applying a LO to Switch B and twist it to HI back again. 37

42 3. Set your pattern generator to square wave with a 1 Hz frequency. Connect the Clock pin to your pattern generator. 4. Now set your Switch A to LO for a second and wait for LED A to light up before twisting back Switch A to HI again. (You should only get one LED A that will light up before it is shifted to LED B). 5. Complete the Table 6.2 on what you have observed from your LED outputs. Demonstrate and verify with your instructor upon completion of your system. Clock OUTPUT LED Pulse A B C D Initial Stage Table 6.2 : Ring Counter Operation REPORT REQUIREMENT The lab report should include the following: 1. Summary of each experiment done. 2. Discussions on each experiments. 3. Remarks on any possible failures and measures done to overcome this problem. 4. Conclusion for the experiments. 38

43 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME: COURSE: MATRIC NO.: TABLE NO.: EXPERIMENT TITLE: Part A : Shift Register Operation Clock OUTPUT LED Switch A Pulse A B C D Initial Stage st 1 2 nd 1 3 rd 1 4 th 1 5 th 0 6 th 0 7 th 0 8 th 0 9 th 1 10 th 0 11 th 1 12 th 1 13 th 0 14 th 0 15 th 0 16 th 1 Table 6.1 : Shift Register Operation Construction Complete? : YES / NO Shift Register Function? : YES / NO Instructor Signature : 39

44 Part B : Ring Counter Operation Clock OUTPUT LED Pulse A B C D Initial Stage Table 6.2 : Ring Counter Operation Construction Complete? : YES / NO Shift Register Function? : YES / NO Instructor Signature : EXERCISES: 1. Explain two advantages and disadvantages for a data transfer by serial shift and parallel shift. 2. Give one example where Ring Counters are applied and briefly explain its operation. 3. Briefly define Johnson Shift Register and its application. 40

45 LAB 7: COUNTER DESIGN OBJECTIVE 1. To design a synchronous counter using J-K flip-flops. EQUIPMENT/COMPONENTS A DC power supply capable of 5V DC output A pattern generator for square wave signals A multimeter Logic Gate IC : 7408 (1pc), 7447 (1pc), 7476 (2pc) Seven Segment Display (1pc) Resistors : 330Ω (1pc) Toggle Switch (1pc) INTRODUCTION Counters are classified into two broad categories according to the way they are clocked: asynchronous and synchronous. In asynchronous counters, the first flip-flop is clocked by the external clock pulse, and then each successive flip-flop is clocked by the output of the preceding flip-flop. However, in synchronous counters, all flip-flops will be connected to the same clock input so that they are clocked simultaneously. Our focus is to design the synchronous counter. Synchronous counter design is also known as sequential circuit design. Figure 7.1 illustrate the general idea of clocked sequential circuit. It can be noticed that there is a clock input to the memory section. Figure 7.1: General Clocked Sequential Circuit Several methods exist for designing counters that follow arbitrary sequences. One common method is using J-K flip-flop in a synchronous counter configuration. The basic idea is to design the logic circuits that decode the various states of the counter to supply the logic levels to each J and K input by applying the transition table as shown in Table

46 Output Transitions FF Inputs Q(t) Q(t+1) J K X X 1 0 X X 0 Table 7.1: J-K flip-flop excitation table As usual, you will be given a design problem. It is an advantage for you to master the synchronous counter design technique using J-K flip-flop before attending the lab session. PROCEDURE Flip-flop Counter Design 1. Design a binary counter with sequence shown on the state transition diagram in Figure 7.2. Figure 7.2: Counting Sequence 2. You will need to determine the following : a. Create the circuit excitation table as in Ttable 7.2 based on the given state transitions in Table 7.1 above. b. Create your Karnaugh Map for a J-K flip-flop to generate the required inputs for the flip-flops. (Don t care states can be placed in the corresponding invalid cells.) c. Draw the circuit diagram to implement the expressions derived from your K- Map. 42

47 3. Construct the circuit you have drawn. Put a Switch A to your CLR/RESET pin for all your flip-flops. (Make sure your PRE pins are set to HI to disable the PRE/SET function). 4. Assign a clock pulse (square waveform) from a pattern generator with a frequency of 1 Hz to your counter. 5. Justify your design and demonstrate to your instructors for verification. REPORT REQUIREMENT The lab report should include the following: 1. Summary of each step done. 2. Discussions of your design. 3. Remarks on any possible failures during construct and measures done to overcome this problem. 4. Conclusion for the experiment. 43

48 EKT 121 DIGITAL ELECTRONICS I EXPERIMENT DATA SHEET NAME: COURSE: MATRIC NO.: TABLE NO.: EXPERIMENT TITLE: Flip-flop Counter Design OUTPUT VALUES INPUT VALUES Decimal Binary Binary Present Present State Next State Flip-flop 2 Flip-flop 1 Flip-flop 0 Value Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 J 2 K 2 J 1 K 1 J 0 K 0 Table 7.2: JK Flip-flop Counter Excitation Table INSTRUCTOR AREA Check to confirm: Attachment: Counter Karnaugh Map and Boolean Expressions Attachment: Counter Circuit Diagram with 7476 and 7447 ICs included Circuit construction completed Counter operational shown on seven segment display Instructor Signature: 44

49 REFERENCES 1. William Kleitz. (July 14, 2004), Digital Electronics: A Practical Approach. 7 th Edition. Prentice Hall. 45