DG411, DG412, DG413. Monolithic Quad SPST, CMOS Analog Switches. Features. Applications FN Data Sheet June 20, 2007

Transcription

1 DG411, DG412, DG413 Data Sheet FN Monolithic Quad SPST, MOS Analog Switches The DG411 series monolithic MOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole throw (SPST) analog switches, and TTL and MOS compatible digital inputs. These switches feature lower analog ON-resistance (<35Ω) and faster switch time (t ON <175ns) compared to the DG211 or DG212. harge injection has been reduced, simplifying sample and hold applications. The improvements in the DG411 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older MOS technologies. The 44V maximum voltage range permits controlling 40V P-P signals. Power supplies may be single-ended from +5V to 44V, or split from ±5V to ±20V. The four switches are bilateral, equally matched for A or bidirectional signals. The ON-resistance variation with analog signals is quite low over a ±15V analog input range. The switches in the DG411 and DG412 are identical, differing only in the polarity of the selection logic. Two of the switches in the DG413 (#2 and #3) use the logic of the DG211 and DG411 (i.e., a logic 0 turns the switch ON) and the other two switches use DG212 and DG412 positive logic. This permits independent control of turn-on and turn-off times for SPDT configurations, permitting break-before-make or makebefore-break operation with a minimum of external logic. Features ON-Resistance (Max) Ω Low Power onsumption (P D ) <35µW Fast Switching Action - t ON (Max) ns - t OFF (Max) ns Low harge Injection Upgrade from DG211, DG212 TTL, MOS ompatible Single or Split Supply Operation Pb-Free Plus Anneal Available (RoHS ompliant) Applications Audio Switching Battery Operated Systems Data Acquisition Hi-Rel Systems Sample and Hold ircuits ommunication Systems Automatic Test Equipment 1 AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. opyright Intersil Americas Inc. 1993, 1994, 1997, 1999, 2002, All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( ) PAKAGE PKG. DWG. # DG411DJ DG411DJ -40 to Ld PDIP E16.3 DG411DJZ (Note) DG411DJZ -40 to Ld PDIP** (Pb-free) E16.3 DG411DY* DG411DY -40 to Ld SOI (150 mil) M16.15 DG411DYZ* (Note) DG411DYZ -40 to Ld SOI (150 mil) (Pb-free) M16.15 DG411DVZ* (Note) DG411 DVZ -40 to Ld TSSOP (4.4mm) (Pb-free) M DG412DJ DG412DJ -40 to Ld PDIP E16.3 DG412DJZ (Note) DG412DJZ -40 to Ld PDIP** (Pb-free) E16.3 DG412DY* DG412DY -40 to Ld SOI (150 mil) M16.15 DG412DYZ* (Note) DG412DYZ -40 to Ld SOI (150 mil) (Pb-free) M16.15 DG412DVZ* (Note) DG412 DVZ -40 to Ld TSSOP (4.4mm) (Pb-free) M DG413DJ DG413DJ -40 to Ld PDIP E16.3 DG413DJZ (Note) DG413DJZ -40 to Ld PDIP** (Pb-free) E16.3 DG413DY* DG413DY -40 to Ld SOI (150 mil) M16.15 DG413DYZ* (Note) DG413DYZ -40 to Ld SOI (150 mil) (Pb-free) M16.15 DG413DVZ* (Note) DG413 DVZ -40 to Ld TSSOP (4.4mm) (Pb-free) M *Add -T suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-020. Pinout TRUTH TABLE DG411 DG412 DG413 SWITH SWITH LOGI SWITH SWITH 1, 4 2, 3 0 On Off Off On 1 Off On On Off NOTE: Logic 0 0.8V. Logic 1 2.4V. DG411, DG412, DG413 (16 LD PDIP, SOI, TSSOP) TOP VIEW S 1 S 4 D 4 IN IN 2 15 D 2 14 S V L 11 S 3 10 D 3 9 IN 3 Pin Descriptions PIN SYMBOL DESRIPTION 1 Logic ontrol for Switch 1. 2 Drain (Output) Terminal for Switch 1. 3 S 1 Source (Input) Terminal for Switch 1. 4 Negative Power Supply Terminal. 5 Ground Terminal (Logic ommon). 6 S 4 Source (Input) Terminal for Switch 4. 7 D 4 Drain (Output) Terminal for Switch 4. 8 IN 4 Logic ontrol for Switch 4. 9 IN 3 Logic ontrol for Switch D 3 Drain (Output) Terminal for Switch S 3 Source (Input) Terminal for Switch V L Logic Reference Voltage. 13 Positive Power Supply Terminal (Substrate). 14 S 2 Source (Input) Terminal for Switch D 2 Drain (Output) Terminal for Switch IN 2 Logic ontrol for Switch 2. 2 FN

3 Functional Diagrams Four SPST Switches per Package Switches Shown for Logic 1 Input DG411 DG412 DG413 S 1 S 1 S 1 S 2 S 2 S 2 IN 2 IN 2 IN 2 D 2 S 3 D 2 S 3 D 2 S 3 IN 3 IN 3 IN 3 D 3 S 4 D 3 S 4 D 3 S 4 IN 4 IN 4 IN 4 D 4 D 4 D 4 Schematic Diagram (1 hannel) S V L IN X D 3 FN

4 Absolute Maximum Ratings to V to V V L ( -0.3V) to () +0.3V Digital Inputs, V S, V D (Note 1)..... () -2V to () + 2V or 30mA, Whichever Occurs First ontinuous urrent (Any Terminal) mA Peak urrent, S or D (Pulsed 1ms, 10% Duty ycle Max).. 100mA Operating onditions Voltage Range ±20V (Max) Temperature Range to +85 Input Low Voltage V (Max) Input High Voltage V (Min) Input Rise and Fall Time ns Thermal Information Thermal Resistance (Typical, Note 2) θ JA ( /W) PDIP Package* SOI Package TSSOP Package Maximum Junction Temperature (Plastic Packages) Maximum Storage Temperature Range to +150 Pb-free reflow profile see link below (SOI and TSSOP - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. AUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Signals on S X, D X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test onditions: = +15V, = -15V, V L = 5V, V IN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified. PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP (Note 5) MAX UNITS DYNAMI HARATERISTIS Turn-ON Time, t ON R L = 300Ω, L = 35pF, V S = ±10V (Figure 1) ns ns Turn-OFF Time, t OFF ns ns Break-Before-Make Time Delay DG413 Only, R L = 300Ω, L = 35pF (Figure 2) ns harge Injection, Q (Figure 3) L = 10nF, V G = 0V, R G = 0Ω p OFF Isolation (Figure 5) R L = 50Ω, L = 5pF, f = 1MHz db rosstalk (hannel-to-hannel), (Figure 4) db Source OFF apacitance, S(OFF) f = 1MHz (Figure 6) pf Drain OFF apacitance, D(OFF) pf hannel ON apacitance, pf D(ON) + S(ON) DIGITAL INPUT HARATERISTIS Input urrent V IN Low, I IL V IN Under Test = 0.8V, All Others = 2.4V Full μa Input urrent V IN High, I IH V IN Under Test = 2.4V, All Others = 0.8V Full μa ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG I S = 10mA Full V ± Drain-Source ON Resistance, I S = 10mA, V D = ±8.5V, = 13.5V, = -13.5V Ω r DS(ON) Full Ω ± 4 FN

5 Electrical Specifications Test onditions: = +15V, = -15V, V L = 5V, V IN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified. (ontinued) PARAMETER TEST ONDITIONS TEMP ( ) MIN TYP (Note 5) MAX UNITS Source OFF Leakage urrent, = 16.5V, = -16.5V, V D = ±15.5V, V S = 15.5V ± na I S(OFF) Full na Drain OFF Leakage urrent, ± na I D(OFF) Full na hannel ON Leakage urrent, = 16.5V, = -16.5V, V S = V D = ±15.5V ± na I D(ON) + I S(ON) Full na POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 16.5V, = -16.5V, V IN = 0V or 5V μa μa Negative Supply urrent, I μa μa Logic Supply urrent, I L μa μa Ground urrent, I μa ± μa Electrical Specifications (Single Supply) Test onditions: = +12V, = 0V, V L = 5V, V IN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified. TEMP ( ) MIN TYP (Note 5) MAX PARAMETER TEST ONDITIONS UNITS DYNAMI HARATERISTIS Turn-ON Time, t ON R L = 300Ω, L = 35pF, ns V S = 8V, (Figure 1) ns Turn-OFF Time, t OFF ns ns Break-Before-Make Time Delay DG413 Only, R L = 300Ω, L = 35pF, V S = 8V ns harge Injection, Q L = 10nF, V G = 6.0V, R G = 0Ω p ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full 0-12 V Drain-Source ON-Resistance, r DS(ON) I S = -10mA, V D = 3V, 8V = 10.8V Ω Full Ω 5 FN

6 Electrical Specifications (Single Supply) Test onditions: = +12V, = 0V, V L = 5V, V IN = 2.4V, 0.8V (Note 3), Unless Otherwise Specified. (ontinued) PARAMETER TEST ONDITIONS POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 13.2V, = 0V μa V IN = 0V or 5V μa Negative Supply urrent, I μa μa Logic Supply urrent, I L μa μa Ground urrent, I μa μa NOTES: 3. V IN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Test ircuits and Waveforms V O is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. LOGI INPUT SWITH INPUT SWITH OUTPUT 3V 0V V S 0V 50% V O 90% t OFF t r < 20ns t f < 20ns 90% t ON Repeat test for all IN and S. For load conditions, see Specifications. L includes fixture and stray NOTE: Logic input waveform is inverted for switches that have the capacitance. R L V O = V S opposite logic sense. R L + r DS( ON) FIGURE 1A. MEASUREMENTS POINTS FIGURE 1B. TEST IRUIT FIGURE 1. SWITHING TIMES TEMP ( ) SWITH INPUT LOGI INPUT S 1 MIN TYP (Note 5) +5V +15V V L -15V MAX R L UNITS SWITH OUTPUT V O L LOGI INPUT SWITH OUTPUT (V01) SWITH OUTPUT V O2 3V 0V V S1 0V V S2 0V t D 90% t D FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME 90% S 1 V S1 = 10V S 2 V S2 = 10V LOGI INPUT, IN 2 V L +5V +15V D2 R L2 300Ω -15V L2 35pF FIGURE 2B. TEST IRUITS R V L1 O2 300Ω V O1 L1 35pF L includes fixture and stray capacitance. 6 FN

7 Test ircuits and Waveforms (ontinued) SWITH OUTPUT ΔV O R G V O IN X OFF ON OFF V G L V IN = 3V FIGURE 3A. TEST IRUIT ON OFF Q = ΔV OFF IN O x L X NOTE: IN X dependent on switch configuration, input polarity determined by sense of switch. FIGURE 3B. MEASUREMENT POINTS FIGURE 3. HARGE INJETION +15V +15V SIGNAL GENERATOR 0dBm V S V D 50Ω SIGNAL GENERATOR 0dBm V S 0V, 2.4V IN 2 0V, 2.4V IN X 0V, 2.4V ANALYZER R L V D -15V N ANALYZER R L V D -15V FIGURE 4. ROSSTALK TEST IRUIT FIGURE 5. OFF ISOLATION TEST IRUIT +15V V S IMPEDANE ANALYZER IN X 0V, 2.4V V D f = 1MHz -15V FIGURE 6. SOURE/DRAIN APAITANES TEST IRUIT 7 FN

8 Application Information Single Supply Operation The DG411, DG412, DG413 can be operated with unipolar supplies from 5V to 44V. These devices are characterized and tested for single supply operation at 12V to facilitate the majority of applications. To function properly, 12V is tied to Pins 13 and 0V is tied to Pin 4. Summing Amplifier When driving a high impedance, high capacitance load such as shown in Figure 7, where the inputs to the summing amplifier have some noise filtering, it is necessary to have shunt switches for rapid discharge of the filter capacitor, thus preventing offsets from occurring at the output. Pin 12 still requires 5V for TTL compatible switching. R 1 R 2 V IN1 1 R 5 R 3 R 4 V IN2 - + V OUT 2 R 6 DG413 FIGURE 7. SUMMING AMPLIFIER 8 FN

9 Typical Performance urves r DS(ON) (Ω) A: ±5V B: ±8V : ±10V D: ±12V E: ±15V F: ±20V 5 T A = FIGURE 8. ON RESISTANE vs V D AND POWER SUPPLY VOLTAGE A DRAIN VOLTAGE (V) B D E F t ON, t OFF (ns) = 15V, = -15V V L = 5V, V S = 10V t ON t OFF TEMPERATURE ( ) FIGURE 9. SWITHING TIME vs TEMPERATURE I S, I D (pa) = 15V, = -15V V L = 5V, T A = +25 I D(OFF) I S(OFF) I D(ON) + I S(ON) V S, V D (V) FIGURE 10. LEAKAGE URRENTS vs ANALOG VOLTAGE I SUPPLY 100mA 10mA 1mA 100μA 10μA 1μA = 15V, = -15V V L = 5V 4SW 4SW I+, I- 100nA 1SW 1SW 10nA k 10k 100k 1M 10M FREQUENY (Hz) FIGURE 11. SUPPLY URRENT vs INPUT SWITHING FREQUENY I L Q (p) = 15V, = -15V V L = 5V L = 1nF L = 10nF Q (p) = 15V, = -15V V L = 5V L = 10nF L = 1nF V S (V) FIGURE 12. HARGE INJETION vs SOURE VOLTAGE V D (V) FIGURE 13. HARGE INJETION vs DRAIN VOLTAGE 9 FN

10 Die haracteristics DIE DIMENSIONS: 2760mm x 1780mm x 485mm METALLIZATION: Type: SiAl Thickness: 12kÅ ±1kÅ Metallization Mask Layout DG411, DG412, DG413 PASSIVATION: Type: Nitride Thickness: 8kÅ ±1kÅ WORST ASE URRENT DENSITY: 1.5 x 10 5 A/cm 2 IN 2 (2) (1) (16) (15) D 2 S 1 (3) (14) S 2 (4) (13) SUBSTRATE (5) (12) V L S 4 (6) (11) S 3 (7) (8) (9) (10) D 4 IN 4 IN 3 D 3 10 FN

11 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA (0.002) e D 0.10(0.004) M A M E1 -B- -Ab -- SEATING PLANE A B S E 0.25(0.010) M B A1 NOTES: 1. These package dimensions are within allowable dimensions of JEDE MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm ( inch). 10. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) α GAUGE PLANE 0.10(0.004) A2 M L c M LEAD THIN SHRINK SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c D E e BS 0.65 BS - E L N a 0 o 8 o 0 o 8 o - Rev. 1 2/02 11 FN

12 Dual-In-Line Plastic Packages (PDIP) DG411, DG412, DG413 INDEX AREA N N/2 -B- -A- D E BASE PLANE A2 -- A SEATING PLANE L L D1 A1 e D1 A B1 e e B e B (0.25) M A B S NOTES: 1. ontrolling Dimensions: INH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A1 and L are measured with the package seated in JE- DE seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum e B and e are measured at the lead tips with the leads unconstrained. e must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. N is the maximum number of terminal positions. 10. orner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). E1 E16.3 (JEDE MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , D D E E e BS 2.54 BS - e A BS 7.62 BS 6 e B L N Rev. 0 12/93 12 FN

13 Small Outline Plastic Packages (SOI) DG411, DG412, DG413 N INDEX AREA e D B 0.25(0.010) M A M E -B- -A- -- SEATING PLANE A B S H 0.25(0.010) M B A1 0.10(0.004) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. α L M h x 45 M16.15 (JEDE MS-012-A ISSUE ) 16 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B D E e BS 1.27 BS - H h L N α Rev. 1 6/05 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see 13 FN