Data Sheet June 13, Features TEMP.

Transcription

1 G48, G49 ata Sheet FN Single 8-Channel/ifferential 4-Channel, CMOS Analog Multiplexers The G48 Single 8-Channel, and G49 ifferential 4-Channel monolithic CMOS analog multiplexers are drop-in replacements for the popular G58A and G59A series devices. They each include an array of eight analog switches, a TTL/CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds and an ABLE input for device selection when several multiplexers are present. The G48 and G49 feature lower signal ON resistance (<Ω) and faster switch transition time (t TRANS < 25ns) compared to the G58A or G59A. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the G48 series are made possible by using a high-voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. Power supplies may be single-ended from +5V to +34V, or split from ±5V to ±2V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. Features ON Resistance (Max, 25 C) Ω Low Power Consumption (P ) <mw Fast Switching Action - t TRANS <25ns - t ON/OFF() <5ns Low Charge Injection Upgrade from G58A/G59A TTL, CMOS Compatible Single or Split Supply Operation Pb-Free Plus Anneal Available (RoHS Compliant) Applications ata Acquisition Systems Audio Switching Systems Automatic Testers Hi-Rel Systems Sample and Hold Circuits Communication Systems Analog Selector Switch Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. WG. # G48J G48J -4 to 85 6 Ld PIP E6.3 G48JZ (Note) G48JZ -4 to 85 6 Ld PIP** (Pb-free) E6.3 G48Y* G48Y -4 to 85 6 Ld SOIC M6.5 G48YZ* (Note) G48YZ -4 to 85 6 Ld SOIC (Pb-free) M6.5 G48VZ* (Note) G48VZ -4 to 85 6 Ld TSSOP (Pb-free) M6.73 G49J G49J -4 to 85 6 Ld PIP E6.3 G49JZ (Note) G49JZ -4 to 85 6 Ld PIP** (Pb-free) E6.3 G49Y* G49Y -4 to 85 6 Ld SOIC M6.5 G49YZ* (Note) G49YZ -4 to 85 6 Ld SOIC (Pb-free) M6.5 G49VZ* (Note) G49VZ -4 to 85 6 Ld TSSOP (Pb-free) M6.73 *Add -T suffix for tape and reel. **Pb-free PIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEEC J ST-2. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 993, 994, 997, 999, 24, 26. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 G48, G49 Pinouts G48 (PIP, SOIC, TSSOP) TOP VIEW G49 (PIP, SOIC, TSSOP) TOP VIEW A V- S S 2 S 3 S A 5 A 2 A 2 6 A 5 GN 4 GN V S 5 S 6 S 7 S A S 2A S 3A S 4A S B 2 S 2B S 3B S 4B 9 S 8 A 8 9 B Functional Block iagrams G48 G49 S S A A S 2 ECOER/ RIVER S 4A S B B S 8 S 4B ECOER/ RIVER 5V REF LEVEL SHIFT 5V REF LEVEL SHIFT IGITAL PROTECTION IGITAL PROTECTION A A A 2 A A TRUTH TABLE G48 A 2 A A ON X X X NONE TRUTH TABLE G49 A A ON X X NONE NOTES:. V AH Logic 2.4V. 2. V AL Logic.8V. 8 2 FN3283.8

3 G48, G49 Pin escriptions - (G48) PIN SYMBOL ESCRIPTION A Logic ecode Input (Bit, LSB) 2 Enable Input 3 V- Negative Power Supply Terminal 4 S Source (Input) for Channel 5 S 2 Source (Input) for Channel 2 6 S 3 Source (Input) for Channel 3 7 S 4 Source (Input) for Channel 4 8 rain (Output) 9 S 8 Source (Input) for Channel 8 S 7 Source (Input) for Channel 7 S 6 Source (Input) for Channel 6 2 S 5 Source (Input) for Channel 5 3 Positive Power Supply Terminal (Substrate) 4 GN Ground Terminal (Logic Common) 5 A 2 Logic ecode Input (Bit 2, MSB) 6 A Logic ecode Input (Bit ) Pin escriptions - (G49) PIN SYMBOL ESCRIPTION A Logic ecode Input (Bit, LSB) 2 Enable Input 3 V- Negative Power Supply Terminal 4 S A Source (Input) for Channel a 5 S 2A Source (Input) for Channel 2a 6 S 3A Source (Input) for Channel 3a 7 S 4A Source (Input) for Channel 4a 8 A rain a (Output a) 9 B rain b (Output b) S 4B Source (Input) for Channel 4b S 3B Source (Input) for Channel 3b 2 S 2B Source (Input) for Channel 2b 3 S B Source (Input) for Channel b 4 Positive Power Supply Terminal 5 GN Ground Terminal (Logic Common) 6 A Logic ecode Input (Bit, MSB) 3 FN3283.8

4 G48, G49 Absolute Maximum Ratings to V V GN to V V igital Inputs, V S, V (Note 3)......(V-) -2V to () + 2V or 2mA, Whichever Occurs First Continuous Current (Any Terminal) mA Peak Current, S or (Pulsed ms, % uty Cycle Max).. ma Operating Conditions Temperature Range C to 85 C Thermal Information Thermal Resistance (Typical, Note 4) θ JA ( C/W) PIP Package SOIC Package TSSOP Package Maximum Junction Temperature C Maximum Storage Temperature Range C to 25 C Maximum Lead Temperature (Soldering s) C (SOIC and TSSOP - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on S X, X, or A X exceeding or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 4. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: =, V- =, V AL =.8V, V AH = 2.4V, Unless Otherwise Specified PARAMETER TEST CONITIONS TEMP ( C) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX UNITS YNAMIC CHARACTERISTICS Transition Time, t TRANS (See Figure ) Full ns Break-Before-Make Interval, t OP (See Figure 3) ns Enable Turn-ON Time, t ON() (See Figure 2) ns Full ns Enable Turn-OFF Time, t OFF() (See Figure 2) Full ns Charge Injection, Q C L = nf, V S = V pc OFF Isolation V = V, R L = kω, f = khz (Note 9) db Logic Input Capacitance, C IN f = MHz pf Source OFF Capacitance, C S(OFF) V = V, V S = V, pf f = MHz rain OFF Capacitance, C (OFF) V = V, V = V, G48 f = MHz pf G pf rain ON Capacitance, C (ON) V = 3V, V = V, G48 f = MHz, V A = V or 3V pf G pf IGITAL CHARACTERISTICS Logic Input Current, Input Voltage High, I AH V A = 2.4V, 5V Full - - µa Logic Input Current, Input Voltage Low, I AL V = V, 2.4V, V A = V Full - - µa ANALOG CHARACTERISTICS Analog Signal Range, V ANALOG Full -5-5 V rain-source ON Resistance, r S(ON) V = ±V, I S = -ma (Note 7) 25-4 Ω Full Ω r S(ON) Matching Between Channels, V = V, -V (Note 8) Ω r S(ON) Source OFF Leakage Current, I S(OFF) V = V, V S = ±V, V = +V na Full -5-5 na 4 FN3283.8

5 G48, G49 Electrical Specifications Test Conditions: =, V- =, V AL =.8V, V AH = 2.4V, Unless Otherwise Specified (Continued) PARAMETER TEST CONITIONS TEMP ( C) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX rain OFF Leakage Current, I (OFF) V = V, V = ±V, G48 V S = +V na Full -2-2 na G na Full - - na rain ON Leakage Current, I (ON) V S = V = ±V (Note 7) G na Full -2-2 na G na Full - - na POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V = V, V A = V (Standby) Full - 75 µa Negative Supply Current, I- Full µa Positive Supply Current, I+ V = 2.4V, V A = V ma (Enabled) Full ma Negative Supply Current, I- Full µa UNITS Electrical Specifications Single Supply Test Conditions: = 2V, V- = V, V AL =.8V, V AH = 2.4V, Unless Otherwise Specified PARAMETER TEST CONITION TEMP ( C) (NOTE 5) MIN (NOTE 6) TYP (NOTE 5) MAX UNITS YNAMIC CHARACTERISTICS Switching Time of Multiplexer, t TRANS V S = 8V, V S8 = V, V IN = 2.4V ns Enable Turn-ON Time, t ON() V INH = 2.4V, V INL = V, ns Enable Turn-OFF Time, t OFF() V S = 5V ns Charge Injection, Q C L = nf, V G = V, R G = Ω pc ANALOG CHARACTERISTICS Analog Signal Range, V ANALOG Full - 2 V rain-source ON-Resistance, r S(ON) V = 3V, V, I S = -ma (Note 7) Ω NOTES: 5. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Typical values are for ESIGN AI ONLY, not guaranteed nor production tested. 7. Sequence each switch ON. 8. r S(ON) = r S(ON) (Max) - r S(ON) (Min). 9. Worst case isolation occurs on channel 4 due to proximity to the drain pin. 5 FN3283.8

6 G48, G49 Test Circuits and Waveforms +2.4V +2.4V S ±V S B ±V A S 2 - S 7 A G48 S 8 A 2 GN V- ± V S A - S 4A, A A G49 S 4B A GN V- B ± V 5Ω 3Ω 35pF 5Ω 3Ω 35pF FIGURE A. G48 TEST CIRCUIT FIGURE B. G49 TEST CIRCUIT 3V V V S S ON V V S8 5%.8 V S8 5% t r < 2ns t f < 2ns.8 V S t TRANS S 8 ON t TRANS FIGURE C. MEASUREMT POINTS FIGURE. TRANSITION TIME A S -5V A S B G48 G49 A A S 2 - S 8 S A - S 4A A V 2 IN VIN S 2B - S 4B, A V GN V- O GN V- B 5Ω 3Ω 35pF 5Ω 3Ω -5V V o 35pF FIGURE 2A. G48 TEST CIRCUIT FIGURE 2B. G49 TEST CIRCUIT V IN 3V V 5% 5% t r < 2ns t f < 2ns V t ON().9 t OFF() FIGURE 2C. MEASUREMT POINTS FIGURE 2. ABLE ING TIMES 6 FN3283.8

7 G48, G49 Test Circuits and Waveforms (Continued) +2.4V ALL S AN A +5V (V S ) 3V V t r < 2ns t f < 2ns A A A 2 GN G48 G49, B V- V S 8% 8% 5Ω 3Ω 35pF V t OP FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMT POINTS FIGURE 3. BREAK-BEFORE-MAKE INTERVAL R G S X 3V V V G CHANNEL SELECT A A A 2 GN V- C L nf ON OFF IS THE MEASURE VOLTAGE UE TO CHARGE TRANSFER ERROR, Q Q = C L x FIGURE 4A. TEST CIRCUIT FIGURE 4. CHARGE INJECTION FIGURE 4B. MEASUREMT POINTS V 5V SIGNAL GERATOR V IN S X S 8 A 2 A A V- kω kω V IN SIGNAL GERATOR S S X S 8 A 2 A A V- kω GN GN ANALYZER ANALYZER UT OFF ISOLATION = 2 Log V IN UT CROSSTALK = 2 Log V IN FIGURE 5. OFF ISOLATION FIGURE 6. CROSSTALK 7 FN3283.8

8 G48, G49 Test Circuits and Waveforms (Continued) 5V 3R V V IN S SIGNAL GERATOR A 2 A A V- R L CHANNEL SELECT A 2 A A V- S S 8 IMPEANCE ANALYZER GN GN ANALYZER UT INSERTION LOSS = 2 Log V IN FIGURE 7. INSERTION LOSS FIGURE 8. SOURCE/RAIN CAPACITANCES Typical Applications Overvoltage Protection A very convenient form of overvoltage protection consists of adding two small signal diodes (N448, N94 type) in series with the supply pins (see Figure 9). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or below the normal or V- value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference - (V-) doesn t exceed 44V. The addition of these diodes will reduce the analog signal range to V below and V above V-, but it preserves the low channel resistance and low leakage characteristics. Typical application information is for esign Aid Only, not guaranteed and not subject to production testing. V G S X V- N448 G48 N448 FIGURE 9. OVERVOLTAGE PROTECTION USING BLOCKING IOES 8 FN3283.8

9 G48, G49 Typical Performance Curves = V- = C (ON) 2. 5 I IN (pa). C S, (pf) C (OFF).5pA 25. C S(OFF) V IN (V) V A (V) FIGURE. CURRT vs VOLTAGE FIGURE. SOURCE/RAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 2V SUPPLY) 8 6 = V- = C (ON) V SUPPLY = ±5V V IN = V C S, (pf) 4 C (OFF) I IN (pa) C S(OFF) V A (V) FIGURE 2. SOURCE/RAIN CAPACITANCE vs ANALOG VOLTAGE TEMPERATURE ( C) FIGURE 3. CURRT vs TEMPERATURE G48 I (OFF) G49 I (OFF) G49 I (ON) G48 I (ON) 6 2 = 5V V- = V S = -V FOR I (OFF) V = V S(OP) FOR I (ON) I (pa) I (pa) V S = V FOR I (OFF) V S = V FOR I (ON) V (V) FIGURE 4. RAIN LEAKAGE CURRT vs SOURCE/RAIN VOLTAGE (SINGLE 2V SUPPLY) - G49 I (OFF) G49 I (ON) G48 I (ON), I (OFF) V S, V (V) FIGURE 5. RAIN LEAKAGE CURRT vs SOURCE/RAIN VOLTAGE 9 FN3283.8

10 G48, G49 Typical Performance Curves (Continued) = V- = I S(OFF) (pa) 5 V IN (V). -5 = +2V V- = V V S (V) FIGURE 6. SOURCE LEAKAGE CURRT vs SOURCE VOLTAGE V SUPPLY (±V) FIGURE 7. ING THRESHOL vs SUPPLY VOLTAGE 5 4 V SUPPLY = ±5V V SUPPLY = ±5V = 2.4V 2 -(I-) (µa) 2 I+ (ma) = V = 2.4V. = V. K K K M M. k k k M M ING FREQUCY (Hz) ING FREQUCY (Hz) FIGURE 8. NEGATIVE SUPPLY CURRT vs ING FREQUCY FIGURE 9. POSITIVE SUPPLY CURRT vs ING FREQUCY 5 4 I+ V SUPPLY = ±5V 3-2 I+, I- (na) 2 I- (na) -4. -(I-) -6 = 5V V- = V IN = V V = V TEMPERATURE ( C) FIGURE 2. I SUPPLY vs TEMPERATURE TEMPERATURE ( C) FIGURE 2. NEGATIVE SUPPLY CURRT vs TEMPERATURE FN3283.8

11 G48, G49 Typical Performance Curves (Continued) 2 5 = 5V V- = V IN = V V = V C L =,pf V IN = 5V P-P = 5V V- = I+ (µa) Q (pc) TEMPERATURE ( C) - = 2V V- = V V S (V) 5 FIGURE 22. POSITIVE SUPPLY CURRT vs TEMPERATURE (G48) FIGURE 23. CHARGE INJECTION vs ANALOG VOLTAGE 2 6 ±5V 4 2 = 7.5V r S(ON) (Ω) ±8V ±V ±2V r S(ON) (Ω) 8 6 V 2V 5V 2V 2 ±5V ±2V V (V) V V- = V V (V) FIGURE 24. r S(ON) vs V AN SUPPLY FIGURE 25. r S(ON) vs V (SINGLE SUPPLY) = 5V V- = 25 C r S(ON) (Ω) C 85 C 25 C r S(ON) (Ω) C 25 C 2 C -4 C -55 C -5 5 V S (V) C 3-4 C -55 C = 2V V- = V V S (V) FIGURE 26. r S(ON) vs V S AN TEMPERATURE FIGURE 27. r S(ON) vs V S AN TEMPERATURE (SINGLE SUPPLY) FN3283.8

12 G48, G49 Typical Performance Curves (Continued) = V- = R L = kω (db) -9 OFF ISOLATION t (ns) 2 75 t TRANS -7 5 t OFF() -5 CROSSTALK 25 t ON() -3 k k k M M M FREQUCY (Hz) FIGURE 28. OFF ISOLATION AN CROSSTALK vs FREQUCY V SUPPLY (V) FIGURE 29. ING TIME vs SINGLE SUPPLY 2 9 t TRANS 75 t TRANS t ON() t (ns) t (ns) 25 3 t OFF() t OFF() t ON() V SUPPLY (±V) FIGURE 3. ING TIME vs BIPOLAR SUPPLY V IN (V) FIGURE 3. ING TIME vs V IN (SINGLE SUPPLY) 8 6 t TRANS R L = kω t (ns) 4 2 LOSS (db) = V- = REF. V RMS t OFF() -4 t ON() -5 R L = 5Ω V IN (V) FIGURE 32. ING TIME vs V IN (BIPOLAR SUPPLY) FREQUCY (Hz) FIGURE 33. INSERTION LOSS vs FREQUCY 2 FN3283.8

13 G48, G49 ie Characteristics IE IMSIONS: 8µm x 332µm x 485µm METALLIZATION: Type: SiAl Thickness: 2kÅ ±kå PASSIVATION: Type: Nitride Thickness: 8kÅ ±kå WORST CASE CURRT SITY: 9. x 4 A/cm 2 Metallization Mask Layout G48 A A A 2 GN (2) () (6) (5) (4) NC V- (3) (3) S (4) (2) S 5 S 2 (5) () S 6 S 3 (6) NC S 4 (7) (8) (9) S 8 () S 7 3 FN3283.8

14 G48, G49 ie Characteristics IE IMSIONS: 8µm x 332µm x 485µm METALLIZATION: Type: SiAl Thickness: 2kÅ ±kå PASSIVATION: Type: Nitride Thickness: 8kÅ ±kå WORST CASE CURRT SITY: 9. x 4 A/cm 2 Metallization Mask Layout G49 A A GN (2) () (6) NC (5) NC V- (3) (4) S A (4) (3) S B S 2A (5) (2) S 2B S 3A (6) () S 3B S 4A (7) (8) A (9) B () S 4B 4 FN3283.8

15 G48, G49 Thin Shrink Small Outline Plastic Packages (TSSOP) N INEX AREA 2 3.5(.2) e.(.4) M C A M E -B- -Ab -C- SEATING PLANE A B S E.25(.) M B A NOTES:. These package dimensions are within allowable dimensions of JEEC MO-53-AB, Issue E. 2. imensioning and tolerancing per ANSI Y4.5M imension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side. 4. imension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. imension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α GAUGE PLANE.(.4).25. A2 M L c M LEA THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c E e.26 BSC.65 BSC - E L N α o 8 o o 8 o - Rev. 2/2 5 FN3283.8

16 G48, G49 ual-in-line Plastic Packages (PIP) INEX AREA N 2 3 N/2 -B- -A- E BASE PLANE A2 -C- A SEATING PLANE L C L A e A B e e C C B e B. (.25) M C A B S NOTES:. Controlling imensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. imensioning and tolerancing per ANSI Y4.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No imensions A, A and L are measured with the package seated in JE- EC seating plane gauge GS-3. 5.,, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. ambar protrusions shall not exceed. inch (.25mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/2 and N/2 + ) for E8.3, E6.3, E8.3, E28.3, E42.6 will have a B dimension of inch ( mm). E E6.3 (JEEC MS--BB ISSUE ) 6 LEA UAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C E E e. BSC 2.54 BSC - e A.3 BSC 7.62 BSC 6 e B L N Rev. 2/93 6 FN3283.8

17 Small Outline Plastic Packages (SOIC) G48, G49 N INEX AREA 2 3 e B.25(.) M C A M E -B- -A- -C- SEATING PLANE A B S H.25(.) M B A.(.4) NOTES:. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number imensioning and tolerancing per ANSI Y4.5M imension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side. 4. imension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.24 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α L M h x 45 C M6.5 (JEEC MS-2-AC ISSUE C) 6 LEA NARROW BOY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C E e.5 BSC.27 BSC - H h L N α Rev. 6/5 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 7 FN3283.8