HI-506, HI-507, HI-508, HI-509

Transcription

1 HI-506, HI-507, HI-508, HI-509 Data Sheet FN Single 16 and 8/Differential 8-Channel and 4-Channel CMOS nalog Multiplexers The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see pplication Notes N520 and N521). The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic 1 and maximum 0.8V for logic 0. This allows direct interface without pullup resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200Ω resistor and diode clamp to each supply. The HI-506 is a single 16-channel, the HI-507 is an 8-channel differential, the HI-508 is a single 8-channel and the HI-509 is a 4-channel differential multiplexer. If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. Ordering Information PRT NUMBER TEMP. RNGE ( o C) PCKGE PKG. DWG. # HI to Ld CERDIP F28.6 HI to Ld CERDIP F28.6 HI4P to Ld PLCC N28.45 HI4P0506-5Z (See Note) 0 to Ld PLCC (Pb-free) N28.45 HI9P to Ld SOIC M28.3 HI9P0506-9Z (See Note) -40 to Ld SOIC (Pb-free) M28.3 HI to Ld CERDIP F28.6 HI to Ld PDIP E28.6 HI to Ld CERDIP F16.3 HI to Ld CERDIP F16.3 HI to Ld PDIP E16.3 HI Z (See Note) 0 to Ld PDIP (Pb-free) E16.3 HI9P to Ld SOIC M16.15 HI9P0508-5Z (See Note) 0 to Ld SOIC (Pb-free) M16.15 Features Pb-Free vailable (RoHS Compliant) (See Ordering Info) Low ON Resistance Ω Wide nalog Signal Range ±15V TTL/CMOS Compatible ccess Time ns Maximum Power Supply V Break-Before-Make Switching No Latch-Up Replaces DG506/DG506 and DG507/DG507 Replaces DG508/DG508 and DG509/DG509 pplications Data cquisition Systems Precision Instrumentation Demultiplexing Selector Switch Ordering Information PRT NUMBER HI9P to Ld SOIC M16.15 HI9P0508-9Z (See Note) -40 to Ld SOIC (Pb-free) M16.15 HI to Ld CERDIP F16.3 HI to Ld CERDIP F16.3 HI to Ld CERDIP F16.3 HI to Ld PDIP E16.3 HI4P to Ld PLCC N20.35 HI4P0509-5Z (See Note) TEMP. RNGE ( o C) PCKGE 0 to Ld PLCC (Pb-free) PKG. DWG. # N20.35 HI9P to Ld SOIC M16.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 1 CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil mericas Inc. Copyright Intersil mericas Inc ll Rights Reserved ll other trademarks mentioned are the property of their respective owners.

2 Pinouts HI-506 (CERDIP, SOIC) TOP VIEW HI-506 (PLCC) TOP VIEW +V SUPPLY V SUPPLY IN 16 +V SUPPLY -V SUPPLY IN 8 IN IN 8 IN 7 IN IN 7 IN 15 IN 14 IN 13 IN IN 6 IN 5 IN 4 IN 3 IN 14 IN 13 IN IN 6 IN 5 IN 4 IN IN 2 IN IN 3 IN 10 IN IN 1 ENBLE DDRESS 0 DDRESS 1 IN 10 IN IN 2 IN 1 DDRESS DDRESS ENBLE HI-507 (PDIP, CERDIP) TOP VIEW HI-508 (PDIP, CERDIP, SOIC) TOP VIEW +V SUPPLY 1 28 B V SUPPLY IN 8B IN 7B IN 6B IN 5B IN 4B IN 3B IN 2B IN 1B IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN 1 ENBLE 0 ENBLE -V SUPPLY IN 1 IN 2 IN 3 IN V SUPPLY IN 5 IN 6 IN 7 IN DDRESS DDRESS DDRESS 2 2 FN3142.6

3 Pinouts (Continued) HI-509 (PDIP, CERDIP, SOIC) TOP VIEW HI-509 (PLCC) TOP VIEW ENBLE 0 1 ENBLE V SUPPLY IN 1 IN 2 IN 3 IN V SUPPLY IN 1B IN 2B IN 3B IN 4B -V SUPPLY IN 1 IN V SUPPLY IN 1B IN 2B 8 9 B IN IN 3B IN 4 B IN 4B 3 FN3142.6

4 Truth Tables HI EN ON CHNNEL X X X X L None L L L L H 1 L L L H H 2 L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 HI EN ON CHNNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 HI EN ON CHNNEL PIR X X L None L L H 1 L H H 2 H L H 3 H H H 4 HI EN ON CHNNEL X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 4 FN3142.6

5 Functional Diagrams HI-506 HI-507 IN 1 IN 1 IN 2 DECODER/ DRIVER IN 8 IN 1B B IN 16 5V REF LEVEL SHIFT IN 8B DECODER/ DRIVER DIGITL INPUT PROTECTION EN 5V REF DIGITL INPUT PROTECTION LEVEL SHIFT EN HI-508 HI-509 IN 1 IN 1 IN 2 DECODER/ DRIVER IN 4 IN 1B B IN 8 5V REF LEVEL SHIFT IN 4B DECODER/ DRIVER DIGITL INPUT PROTECTION EN 5V REF DIGITL INPUT PROTECTION LEVEL SHIFT 0 1 EN 5 FN3142.6

6 Schematic Diagrams DDRESS DECODER V+ P P P P P P P N N N TO P-CHNNEL DEVICE OF THE SWITCH 0 OR 0 N 2 OR 2 1 OR 1 N N TO N-CHNNEL DEVICE OF THE SWITCH 3 OR 3 N ENBLE DELETE 3 OR 3 INPUT FOR HI-507, HI-508, HI-509 DELETE 2 OR 2 INPUT FOR HI-509 V- DDRESS INPUT BUFFER LEVEL SHIFTER P3 V+ V+ D1 P1 N1 P4 P5 P6 P7 P8 P9 P10 200Ω D2 V L V R P2 N4 N6 N7 N8 N9 N10 V- N2 N5 IN N3 V- LL N-CHNNEL BODIES TO V- LL P-CHNNEL BODIES TO V+ UNLESS OTHERWISE INDICTED TTL REFEREE CIRCUIT MULTIPLEX SWITCH P15 Q1P Q2P Q3P V+ Q4P FROM DECODE N18 Q5N Q6N Q8N IN V+ N19 N17 V L N12 R2 16.8K P17 Q11P Q7P Q10N Q9P N13 N14 N15 D3 R3 6.8K Q12N P16 V R P18 V- V- FROM DECODE 6 FN3142.6

7 bsolute Maximum Ratings V+ to V V V+ to v V- to V Digital Input Voltage (V EN, V )..... (V-) -4V to (V+) +4V or 20m, Whichever Occurs First nalog Signal (V IN, V, Note 2) (V-) -2V to (V+) +2V Continuous Current, In or Out m Peak Current, In or Out (Pulsed 1ms, 10% Duty Cycle Max). 40m Operating Conditions Temperature Ranges HI-50X o C to 125 o C HI-50X o C to 85 o C HI-50X o C to 75 o C HI-50X o C to 85 o C Typical Minimum Supply Voltage ±10V or Single 20V Thermal Information Thermal Resistance (Typical, Note 1) θ J ( o C/W) θ JC ( o C/W) 16 Ld CERDIP Package Ld SOIC Package N/ 16 Ld PDIP Package N/ 20 Ld PLCC Package N/ 28 Ld CERDIP Package Ld PDIP Package N/ 28 Ld SOIC Package N/ 28 Ld PLCC Package N/ Maximum Junction Temperature Ceramic Packages o C Plastic Packages o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC and PLCC - Lead Tips Only) CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θ J is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Signals on IN or exceeding V+ or V- are clamped by internal diodes. Limit resulting current to maximum current ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Intersil HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. Electrical Specifications Supplies = +15V, -15V; V H (Logic Level High) = 2.4V; V L (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST TEMP -2-4, -5, -9 PRMETER CONDITIONS ( o C) MIN TYP MX MIN TYP MX UNITS DYNMIC CHRCTERISTICS ccess Time, t ns Full ns Break-Before-Make Delay, t OPEN ns Enable Delay (ON), t ON(EN) ns Full ns Enable Delay (OFF), t OFF(EN) ns Full ns Settling Time, t S To 0.1% µs (HI-506 and HI-507) To 0.01% µs Settling Time, t S To 0.1% ns (HI-508 and HI-509) To 0.01% ns Off Isolation Note db Channel Input Capacitance, C S(OFF) pf Channel Output Capacitance, C D(OFF) HI pf HI pf HI pf HI pf Digital Input Capacitance, C pf Input to Output Capacitance, C DS(OFF) pf DIGITL INPUT CHRCTERISTICS Input Low Threshold, V L Full V Input High Threshold, V H Full V Input Leakage Current (High or Low), I Note 5 Full µ 7 FN3142.6

8 Electrical Specifications Supplies = +15V, -15V; V H (Logic Level High) = 2.4V; V L (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued) TEST TEMP -2-4, -5, -9 PRMETER CONDITIONS ( o C) MIN TYP MX MIN TYP MX UNITS NLOG CHNNEL CHRCTERISTICS nalog Signal Range, V IN Full V On Resistance, r ON Note Ω r ON, (ny Two Channels) % Off Input Leakage Current, I S(OFF) Note n Full n Off Output Leakage Current, Note n I D(OFF ) HI-506 Full n HI-507 Full n HI-508 Full n HI-509 Full n On Channel Leakage Current, I D(ON) Note n HI-506 Full n HI-507 Full n HI-508 Full n HI-509 Full n Differential Off Output Leakage Current, I DIFF Full n (HI-507, HI-509 Only) POWER SUPPLY CHRCTERISTICS Current, I+ HI-506/HI-507 Note 7 Full m HI-508/HI-509 Note 7 Full m Current, I- HI-506/HI-507 Note 7 Full m HI-508/HI-509 Note 7 Full m Power Dissipation, P D HI-506/HI-507 Full mw HI-508/HI-509 Full mw NOTES: 3. V = ±10V, I = +1m n is the practical lower limit for high speed measurement in the production test environment. 5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1n at 25 o C. 6. V EN = 0.8V, R L = 1K, C L = 15pF, V S = 7V RMS, f = 100kHz. 7. V EN, V = 0V or 2.4V. Test Circuits and Waveforms T = 25 o C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified 1m V 2 IN V IN ron = V 2 1m FIGURE 1. TEST CIRCUIT 8 FN3142.6

9 Test Circuits and Waveforms T = 25 o C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) ON RESISTE (Ω) o C 25 o C -55 o C NORMLIZED RESISTE (REFERRED TO VLUE T ±15V) o C TO 125 o C V IN = 0V NLOG INPUT (V) SUPPLY VOLTGE (±V) FIGURE 1B. ON RESISTE vs NLOG INPUT VOLTGE FIGURE 1C. NORMLIZED ON RESISTE vs SUPPLY VOLTGE FIGURE 1. ON RESISTE 100n 10n OFF PUT LEKGE CURRENT I D(OFF) LEKGE CURRENT 1n 100p I D(ON) OFF INPUT LEKGE CURRENT I S(OFF) ±10V EN 0.8V I D(OFF) +10V 10p TEMPERTURE ( o C) FIGURE 2. LEKGE CURRENT vs TEMPERTURE FIGURE 2B. I D(OFF) TEST CIRCUIT (NOTE 8) I S(OFF) EN 0.8V 0 1 EN I D(ON) ±10V +10V +10V ±10V 2.4V FIGURE 2C. I S(OFF) TEST CIRCUIT (NOTE 8) FIGURE 2D. I D(ON) TEST CIRCUIT (NOTE 8) FIGURE 2. LEKGE CURRENTS NOTE: 8. Two measurements per channel: ±10V and +10V. (Two measurements per device for I D(OFF) ±10V and +10V) 9 FN3142.6

10 Test Circuits and Waveforms T = 25 o C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) o C SWITCH CURRENT (m) o C 25 o C ±V IN VOLTGE CROSS SWITCH (±V) FIGURE 3. ON CHNNEL CURRENT vs VOLTGE FIGURE 3. ON CHNNEL CURRENT FIGURE 3B. TEST CIRCUIT 8 +15V/+10V +I SUPPLY V SUPPLY = ±15V SUPPLY CURRENT (m) K V SUPPLY = ±10V 10K 100K 1M 10M TOGGLE FREQUEY (Hz) V 50Ω 3.5V EN HIGH = 3.5V V LOW = 0V 50% DUTY CYCLE Similar connection for HI-507/ HI-508/HI-509 V+ 3 IN 1 HI IN 2 THRU 1 IN 7/15 0 IN 8/16 V- -I SUPPLY -15V/-10V ±10V/±5V +10V/+5V MΩ pf FIGURE 4. SUPPLY CURRENT vs TOGGLE FREQUEY FIGURE 4. DYNMIC SUPPLY CURRENT FIGURE 4B. TEST CIRCUIT 10 FN3142.6

11 Test Circuits and Waveforms T = 25 o C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) +15V V+ IN 1 ±10V CCESS TIME (ns) V 50Ω 3.5V 2 IN 2 THRU IN 7/15 1 HI IN 16 EN V- +10V kω pf -15V LOGIC LEVEL (HIGH) (V) Similar connection for HI-507/ HI-508/HI-509 FIGURE 5. CCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 5B. TEST CIRCUIT 50% 3.5V DDRESS DRIVE (V ) 0V V INPUT 2V/DIV. S 1 ON +10V 10% PUT -10V PUT 5V/DIV. t S 16 ON FIGURE 5C. MESUREMENT POINTS FIGURE 5. CCESS TIME 200ns/DIV. FIGURE 5D. WVEFORMS +15V 3 2 V+ HI-506 IN 1 +5V V 50Ω 1 IN 2 THRU IN 7/IN 15 IN 8 /16 3.5V 0 EN V- 200Ω V 50pF -15V Similar connection for HI-507/HI-508/HI-509 FIGURE 6. TEST CIRCUIT 11 FN3142.6

12 Test Circuits and Waveforms T = 25 o C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified (Continued) 3.5V V INPUT 2V/DIV. 0V DDRESS DRIVE (V ) S 1 ON S 16 ON PUT PUT 1V/DIV. 50% 50% t OPEN 100ns/DIV. FIGURE 6B. MESUREMENT POINTS FIGURE 6. BREK-BEFORE-MKE DELY FIGURE 6C. WVEFORMS +15V V+ HI-506 IN 1 IN 2 THRU IN 7/IN 15 IN 8 /16 +10V V 50Ω 0 EN V- 200Ω V 50pF -15V Similar connection for HI-507/HI-508/HI-509 FIGURE 7. TEST CIRCUIT 50% 3.5V 50% ENBLE DRIVE (V ) ENBLE DRIVE 2V/DIV. 0V 90% PUT DISBLED ENBLED (S 1 ON) t ON(EN) 10% 0V PUT 2V/DIV. t OFF(EN) 100ns/DIV FIGURE 7B. MESUREMENT POINTS FIGURE 7. ENBLE DELYS FIGURE 7C. WVEFORMS 12 FN3142.6

13 Typical Performance Curves T = 25 o C, V SUPPLY = ±15V, V H = 2.4V, V L = 0.8V, Unless Otherwise Specified INPUT LOGIC THRESHOLD (V) POWER SUPPLY VOLTGE (±V) (V S ), (V D ) OFF ISOLTION (db) V EN = 0V C LOD = 28pF V S = 7V RMS R L = 1K R L = 10M FREQUEY (Hz) FIGURE 8. LOGIC THRESHOLD vs POWER SUPPLY VOLTGE FIGURE 9. OFF ISOLTION vs FREQUEY 3 3 POWER SUPPLY CURRENT (m) 2 1 V EN = 0V V EN = 2.4V POWER SUPPLY CURRENT (m) 2 1 EN = 5V EN = 0V TEMPERTURE ( o C) TEMPERTURE ( o C) FIGURE 10. HI-506/HI-507 FIGURE 10B. HI-508/HI-509 FIGURE 10. POWER SUPPLY CURRENT vs TEMPERTURE 13 FN3142.6

14 Die Characteristics METLLIZTION: Type: Cul Thickness: 16kÅ ±2kÅ SUBSTRTE POTENTIL (NOTE): -V SUPPLY PSSIVTION: Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ WORST CSE CURRENT DENSITY: 1.4 x 10 5 /cm 2 TRNSISTOR COUNT: 421 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -V SUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SUPPLY potential. Metallization Mask Layout HI-506 HI-507 EN EN IN 1 IN 9 IN 1 IN 1B IN 2 IN 10 IN 2 IN 2B IN 3 IN 11 IN 3 IN 3B IN 4 IN 12 IN 4 IN 4B IN 5 IN 13 IN 5 IN 5B IN 6 IN 14 IN 6 IN 6B IN 7 IN 15 IN 7 IN 7B IN 8 IN 16 IN 8 IN 8B -V +V -V +V B 14 FN3142.6

15 Die Characteristics METLLIZTION: Type: Cul Thickness: 16kÅ ±2kÅ SUBSTRTE POTENTIL (NOTE): -V SUPPLY PSSIVTION: Type: Nitride/Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ WORST CSE CURRENT DENSITY: 1.4 x 10 5 /cm 2 TRNSISTOR COUNT: 234 PROCESS: CMOS-DI NOTE: The substrate appears resistive to the -V SUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SUPPLY potential. Metallization Mask Layout HI-508 HI-509 EN EN 0 1 -V SUP +V SUP -V SUP +V SUP IN 1 IN 5 IN 1 IN 1B IN 2 IN 6 IN 2 IN 2B IN 3 IN 3 IN 7 IN 3B IN 4 IN 8 IN 4 B IN 4B 15 FN3142.6

16 Dual-In-Line Plastic Packages (PDIP) HI-506, HI-507, HI-508, HI-509 INDEX RE N N/2 -B- -- D E BSE PLNE 2 -C- SETING PLNE L C L D1 1 e D1 B1 e e C C B e B (0.25) M C B S NOTES: 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per NSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions, 1 and L are measured with the package seated in JE- DEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). E1 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LED DUL-IN-LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES B B , 10 C D D E E e BSC 2.54 BSC - e BSC 7.62 BSC 6 e B L N Rev. 0 12/93 16 FN3142.6

17 Dual-In-Line Plastic Packages (PDIP) HI-506, HI-507, HI-508, HI-509 INDEX RE BSE PLNE SETING PLNE D1 B1 -C- -- N N/2 B D e D1 E1 NOTES: 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per NSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions, 1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). -B (0.25) M C 2 L B S e C E C L e C e B E28.6 (JEDEC MS-011-B ISSUE B) 28 LED DUL-IN-LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES B B C D D E E e BSC 2.54 BSC - e BSC BSC 6 e B L N Rev. 1 12/00 17 FN3142.6

18 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BSE PLNE SETING PLNE S1 b2 ccc M bbb S b C - B C - B S D e D S NOTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per NSI Y14.5M Controlling dimension: IH. E L M c1 e/2 S D S aaa M C - B LED FINISH BSE METL b1 M (b) SECTION - -D- -- Q -C- -Bα S e c D S (c) F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURTION ) 16 LED CERMIC DUL-IN-LINE FRIT SEL PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES b b b b c c D E e BSC 2.54 BSC - e BSC 7.62 BSC - e/ BSC 3.81 BSC - L Q S α 90 o 105 o 90 o 105 o - aaa bbb ccc M , 3 N Rev. 0 4/94 18 FN3142.6

19 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BSE PLNE SETING PLNE S1 b2 ccc M bbb S b C - B C - B S D e D S NOTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per NSI Y14.5M Controlling dimension: IH. E L M c1 e/2 S D S aaa M C - B LED FINISH BSE METL b1 M (b) SECTION - -D- -- Q -C- -Bα S e c D S (c) F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURTION ) 28 LED CERMIC DUL-IN-LINE FRIT SEL PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES b b b b c c D E e BSC 2.54 BSC - e BSC BSC - e/ BSC 7.62 BSC - L Q S α 90 o 105 o 90 o 105 o - aaa bbb ccc M , 3 N Rev. 0 4/94 19 FN3142.6

20 N Small Outline Plastic Packages (SOIC) INDEX RE e D B 0.25(0.010) M C M E -B- -- -C- SETING PLNE B S H 1 µ 0.25(0.010) M B α 0.10(0.004) L M h x 45 o C M16.15 (JEDEC MS-012-C ISSUE C) 16 LED NRROW BODY SMLL LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES B C D E e BSC 1.27 BSC - H h L N α 0 o 8 o 0 o 8 o - Rev. 1 02/02 NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per NSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 20 FN3142.6

21 Small Outline Plastic Packages (SOIC) HI-506, HI-507, HI-508, HI-509 N INDEX RE e D B 0.25(0.010) M C M E -B- -- -C- SETING PLNE B S H (0.004) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per NSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. µ 0.25(0.010) M B α L M h x 45 o C M28.3 (JEDEC MS-013-E ISSUE C) 28 LED WIDE BODY SMLL LINE PLSTIC PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES B C D E e 0.05 BSC 1.27 BSC - H h L N α 0 o 8 o 0 o 8 o - Rev. 0 12/93 21 FN3142.6

22 Plastic Leaded Chip Carrier Packages (PLCC) (1.07) (1.22) PIN (1) IDENTIFIER D1 D (0.51) MX 3 PLCS (0.66) (0.81) C L (1.07) (1.42) (1.27) TP E1 E C L (0.33) (0.53) (0.10) C (0.64) (1.14) R D2/E2 D2/E2 VIEW (0.51) MIN SETING PLNE N20.35 (JEDEC MS-018 ISSUE ) 20 LED PLSTIC LEDED CHIP CRRIER PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES D D D , 5 E E E , 5 N Rev. 2 11/ (1.14) MIN VIEW TYP (0.64) MIN -C- NOTES: 1. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per NSI Y14.5M Dimensions D1 and E1 do not include mold protrusions. llowable mold protrusion is inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions. 22 FN3142.6

23 Plastic Leaded Chip Carrier Packages (PLCC) (1.07) (1.22) PIN (1) IDENTIFIER D1 D (0.51) MX 3 PLCS (0.66) (0.81) C L (1.07) (1.42) (1.27) TP E1 E C L (0.33) (0.53) (0.10) C (0.64) (1.14) R D2/E2 D2/E2 VIEW NOTES: 1. Controlling dimension: IH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per NSI Y14.5M Dimensions D1 and E1 do not include mold protrusions. llowable mold protrusion is inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. N is the number of terminal positions. -C (0.51) MIN SETING PLNE N28.45 (JEDEC MS-018B ISSUE ) 28 LED PLSTIC LEDED CHIP CRRIER PCKGE IHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES D D D , 5 E E E , 5 N Rev. 2 11/ (1.14) MIN VIEW TYP (0.64) MIN ll Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 23 FN3142.6