Description. For Fairchild s definition of Eco Status, please visit:

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1 FSA2357 Low R ON 3:1 Analog Switch Features 10µA Maximum I CCT Current Over an Expanded Control Voltage Range: V IN=2.6V, V CC=4.5V On Capacitance (C ON): 70pF Typical 0.55Ω Typical On Resistance (R ON) -3db Bandwidth: > 120MHz Low Power Consumption (1µA maximum) Packaged in Pb-Free 14-Pin TSSOP and DQFN Priority Enable Control Circuitry Applications HDMI 5V Power Routing, LCD Monitor, TV, and Set-Top Box Cell Phone, PDA, Digital Camera, and Notebook Description July 2009 The FSA2357 is a Double-Pole, Triple Throw (DP3T) multiplexer that routes three dual-channel sources of data or audio under the control of three select pins. The FSA2357 features very low quiescent current, which allows mobile handset applications direct interface with the baseband processor general-purpose I/Os. Typical applications involve switching in portables and consumer applications, such as cell phones, digital cameras, and notebooks with hubs or controllers. IMPORTANT NOTE: For additional information, please contact Ordering Information Part Number Top Mark Eco Status Packing Description FSA2357BQX 2357 Green FSA2357MTCX FSA2357 RoHS 14-Terminal Depopulated very thin Quad Flat-pack No leads (DQFN) 2.5 x 3.0mm, JEDEC MO Lead Thin Shrink Small Outline Package (TSSOP) 4.4mm wide, JEDEC MO-153 For Fairchild s definition of Eco Status, please visit: Analog Symbol 1B0 1B1 1B2 2B0 2B1 2B2 1A 2A Control S0 S1 S2 Figure 1. Analog Symbol FSA2357 Rev

2 Pin Configurations 1B0 Vcc 1B B1 1B2 2B0 2B1 2B V CC S0 S1 1A 2A S2 8 NC 1B1 1B2 2B0 2B1 2B NC Figure 2. TSSOP-14 (Top Through View) Figure 3. DQFN-14 (Top Through View) S0 S1 1A 2A S2 Pin Descriptions Name Description S0, S1, S2 Switch Control Selects 1A, 2A A Data Bus (Common) 1Bn, 2Bn Multiplexed Source inputs Truth Table S0 S1 S2 Function HIGH X X 1B0 = 1A; 2B0 = 2A LOW HIGH X 1B1 = 1A; 2B1 = 2A LOW LOW HIGH 1B2 = 1A; 2B2 = 2A LOW LOW LOW Disconnected (Hi-Z) FSA2357 Rev

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V SW Switch I/O Voltage (1) 1Bn, 2Bn Pins -0.5 V CC V V CNTRL Control Input Voltage (1) S0, S1 Pins V I IK Input Clamp Diode Current -50 ma I SW Switch I/O Current (Continuous) 350 ma I SWPEAK Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle) 500 ma P D Power Dissipation at 85 C DQFN TSSOP µw T STG Storage Temperature Range C T J Maximum Junction Temperature +150 C T L Lead Temperature (Soldering, 10 Seconds) +260 C ESD All Pins 5500 Human Body Model, JEDEC: JESD22-A114 I/O to 8000 V CC to 8000 Charged Device Model, JEDEC-JESD22-C Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V CNTRL Control Input Voltage (V S0:S1) 0 V CC V V SW Switch I/O Voltage 0 V CC V T A Operating Temperature C θ JA Thermal Resistance (Free Air) DQFN-14 TSSOP C/W FSA2357 Rev

4 DC Electrical Characteristics All typical values are at 25ºC unless otherwise specified. Symbol Parameter Conditions V CC (V) T A = - 40 C to +85 C Min. Typ. Max. Analog Signal Range V CC -5.5 V CC V V IK Clamp Diode Voltage 1.2 V V IH V IL Control Input Voltage 2.7 to HIGH 3.6 to Control Input Voltage 2.7 to LOW 3.6 to I IN Control Input Leakage V IN = 0 to V CC 4.5 ±1 µa I NO(0FF) I NC(0N) Off-Leakage Current of Port (1Bn, 2Bn) On-Leakage Current of Port 1Bn, 2Bn 1Bn, 2Bn or 1A, 2A = 0.3V, V CC -0.3V, or Floating 1Bn, 2Bn or 1A, 2A = 0.3V, V CC -0.3V, or Floating R ON Switch On Resistance (2) 2.0V, 2.7V; I ON = -100mA 1Bn or 2Bn = 0V, 0.7V, Figure 4 Unit na na (3) 1Bn or 2Bn = 0.7V, ΔR ON Delta On Resistance V CC, I ON = -100mA R FLAT(ON) I CC I CCT On Resistance Flatness (4) Quiescent Supply Current Increase in Quiescent Supply Current per Control Voltage and V CC 1Bn or 2Bn = 0V, 0.7V, 2.0V, 2.7V; I ON = -100mA Figure 4 V SW = 0 or V CC-0.3 I OUT = to Ω µa V CNTRL = 3.3V µa Notes: 2. R ON measured by the voltage drop between 1Bn (2Bn) and 1A (2A) pins at identical current through the switch. R ON is determined by the lower of the voltage on the two pins. 3. Guaranteed by characterization; not production tested. 4. Flatness is defined as the difference between the maximum and minimum values of on resistance over the specified range of conditions. V Ω Ω FSA2357 Rev

5 AC Electrical Characteristics All typical values are for V CC = 3.3V at 25ºC unless otherwise specified. Symbol Parameter Conditions V CC (V) t ON t OFF Turn-On Time S[0:1] to Output Turn-Off Time S[0:1] to Output V Bn = 1.5V, R L = 50Ω, C L = 35pF Figure 8 V Bn = 1.5V, R L = 50Ω, C L = 35pF Figure 8 t PD Propagation Delay (5) R L = 50Ω, C L = 5pF Figure 9 (5) RL = 50Ω, CL = 5pF t BBM Break-Before-Make V IN1 = V IN2 = V IN3 = 1.5V Q O IRR Xtalk THD BW Charge Injection Off-Isolation Non-Adjacent Channel Crosstalk Total Harmonic Distortion -3db Bandwidth R GEN = 0Ω, C L = 100pF, R L = OPEN Figure 10 f = 100kHz, R L = 50Ω Figure 12 f = 100kHz, R L = 50Ω Figure 13 f = 20Hz to 20kHz, R L = 600Ω,V SW = 0.5V pp Figure 16 R L = 50Ω, C L = 0, 5pF Figure 11 Note: 5. Guaranteed by characterization; not production tested. T A = - 40 C to +85 C Min. Typ. Max. Unit 2.7 to ns 2.7 to ns ns 2.7 to ns 2.7 to pc 2.7 to db 2.7 to db 2.7 to % 2.7 to MHz Capacitance Symbol Parameter Conditions T A = - 40 C to +85 C Typical C IN Control Pin Input Capacitance V CC = 0V 2.75 pf C ON C OFFA C OFFB A/B On Capacitance Port 1A, 2A Off Capacitance Port 1Bn, 2Bn Off Capacitance V CC = 3.3V, S[0:1] = 01, 10, 11, f = 1MHz Figure 15 V CC = 3.3V, S[0:1] = 00 Figure 14 V CC = 3.3V, S[0:1] = 00 Figure 14 Unit 70 pf 42 pf 20 pf FSA2357 Rev

6 Test Diagrams V ON 1B n, 2B n, or 3B n 1A or 2A V IN S0:S1 R ON = V ON /I ON V S0:S1 I ON = 0 or V CC NC I na(off) V IN S0:S1 V Sel = 0 or V CC **Each switch port is tested separately Figure 4. On Resistance Figure 5. Off Leakage A 1Bn or 2Bn 1A or 2A V IN S0:S2 C L R L R L and C L are functions of the application environment (see tables for specific values). C L includes test fixture and stray capacitance. L Figure 6. AC Test Circuit Load t RISE = 2.5ns 1B0 or 2B0 1A or 2A V CC Input - V Sel 90% V CC /2 V IN1 V IN2 V IN3 C L R L 0V 10% 0.9* VOUT 0.9* S0:S2 t BBM R L and C L are functions of the application environment (see tables for specific values). C L includes test fixture and stray capacitance. Figure 7. Break-Before-Make Timing FSA2357 Rev

7 Test Diagrams (Continued) t RISE =2.5ns t FALL =2.5ns V CC 90% 90% Input- V Sel V CC /2 V CC /2 10% 10% V OH 90% 90% Output- V OL t ON t OFF Figure 8. Turn-On / Turn-Off Waveforms t RISE =2.5ns t FALL = 2.5ns V CC 90% 90% Input -V IN 10% V CC /2 V CC /2 10% V OH Output - 50% 50% V OL tplh t phl Figure 9. Switch Propagation Delay Waveforms R GEN nb n na Logic Input V CC Off On Off V GEN R L C L 0V S0:S2 Δ Q = Δ C L Figure 10. Charge Injection Test FSA2357 Rev

8 Test Diagrams (Continued) VS0:S2 R S and R T are functions of the application environment (see tables for specific values). Figure 11. Bandwidth Network Analyzer R S V IN R T V S Network Analyzer R S V S0:S2 R T V IN V S R S and R T are functions of the application environment (see tables for specific values). R T Off -Isolation = 20 Log ( /V IN ) Figure 12. Channel Off Isolation NC Network Analyzer R S V S0:S2 V IN V S R T R T CROSSTALK = 20 Log ( /V IN ) Figure 13. Non-Adjacent Channel-to-Channel Crosstalk FSA2357 Rev

9 Test Diagrams (Continued) 1Bn, 2Bn, or na Capacitance Meter f=1mhz 1Bn, 2Bn, or na Figure 14. S0:S2 V S0:S2 Channel Off Capacitance = 0 or V CC Capacitance Meter f=1mhz 1Bn, 2Bn, or na S0:S2 V S0:S2 =0orV CC 1Bn, 2Bn, or na Figure 15. Channel On Capacitance V CC R GEN V GEN nb n na 10nF S0:S1 R L Figure 16. Total Harmonic Distortion FSA2357 Rev

10 Physical Dimensions Figure Terminal Depopulated Very Thin Quad Flat-Pack, No leads (DQFN) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FSA2357 Rev

11 Physical Dimensions 0.43 TYP TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV R0.09min Figure Lead Thin Shrink Small Outline Package (TSSOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FSA2357 Rev

12 FSA2357 Rev

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