Low-Power, High-Speed CMOS Analog Switches

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1 Low-Power, High-peed MO Analog es G1/3/ -V upply Max Rating 1-V Analog ignal Range On-Resistance r (on) : Low Leakage I (on) : pa Fast ing t ON : ns Ultra Low Power Requirements P :.3 W TTL, MO ompatible ingle upply apability Wide ynamic Range Break-Before-Make ing Action imple Interfacing Audio and Video ing ample-and-hold ircuits Battery Operation Test Equipment Hi-Rel ystems PBX, PABX The G1/3/ monolithic analog switches were designed to provide precision, high performance switching of analog signals. ombining low power (.3 W, typ) with high speed (t ON : ns, typ), the G1 series is ideally suited for portable and battery powered industrial and military applications. Each switch conducts equally well in both directions when on, and blocks up to 3 peak-to-peak when off. On-resistance is very flat over the full 1-V analog range, rivaling JFET performance without the inherent dynamic range limitations. Built on the proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the PT configurations. An epitaxial layer prevents latchup. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. G1 G1 ual-in-line and OI Key L Two PT es per Package Logic OFF 1 ON Logic. V Logic V Rev. F, -ep-99 FaxBack -9-1

2 G1/3/ ual-in-line and OI Key 3 3 L Two PT es per Package Logic W 1, W 2 W 3, W OFF ON 1 ON OFF Logic. V Logic 1 2. V G G ual-in-line and OI Key 3 3 L Two PT es per Package Logic OFF 1 ON Logic. V Logic 1 2. V FaxBack Rev. F, -ep-99

3 G1/3/ Temp Range Package Part Number G1 G to 1-Pin Plastic IP G1J G1AK to 12 1-Pin erip G1AK/3, MEA L- G1AZ/3, M2A to 1-Pin Plastic IP J 1-Pin Narrow OI Y AK to 12 1-Pin erip AK/3, MEA L M2A to 1-Pin Plastic IP GJ 1-Pin Narrow OI GY to 12 1-Pin erip GAK/3, EA L A to V to V (.3 V) to () +.3 V igital Inputs a V, V () 2 V to ( plus 2 V) or 3 ma, whichever occurs first urrent (Any Terminal) ontinuous ma urrent, or (Pulsed 1 ms % duty) ma torage Temperature (AK, AZ uffix) to (J, Y uffix) to 12 Power issipation (Package) b 1-Pin Plastic IP c mw 1-Pin erip d mw 1-Pin OI e mw L- f mw Notes: a. ignals on X, X, or X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to P Board. c. erate mw/ above d. erate 12 mw/ above e. erate. mw/ above f. erate 13 mw/ above -233 Rev. F, -ep-99 FaxBack -9-3

4 G1/3/ Parameter Analog ymbol Test onditions Unless pecified A uffix to 12 uffix to = 1 V, = = V, V = 2. V,. V f Temp b Typ c Min d Max d Min d Max d Unit Analog ignal Range e V ANALOG V rain-ource On-Resistance rain-ource On-Resistance Off Leakage urrent hannel On Leakage urrent igital ontrol r (on) r (on) I = ma, V = V = 13. V, = 13. V I = ma, V = V, = 1. V, = 1. V I (off) = 1., = 1. V I (off) V = 1. V, V = 1. V I (on) = 1. V, = 1. V V = V = 1. V V Input urrent V Low I under test =. V IL All Other = 2. V V Input urrent V High I under test = 2. V IH All Other =. V ynamic haracteristics Hot Hot Hot Turn-On Time t ON RL = 3 = 3 pf L, L Turn-Off Time t ee Figure 2 OFF Break-Before-Make Time elay () harge Injection t R L = 3, L = 3 pf 12 Q L =, pf V gen =, R gen = Off Isolation Reject Ratio OIRR R = = pf 2 L, L hannel-to-hannel rosstalk X f = 1 MHz TALK 9 na A p ource Off apacitance (off) 12 rain Off apacitance (off) f = 1 MHz, V = 12 pf hannel On apacitance, (on) 39 Power upplies Positive upply urrent I+ Negative upply urrent I = 1. V, = 1. V V = or V Logic upply urrent I L Ground urrent I Notes: a. Refer to PROE OPTION FLOWHART. b. = 2, = as determined by the operating temperature suffix. c. Typical values are for EIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V = input voltage to perform proper function ns db AA FaxBack Rev. F, -ep-99

5 G1/3/ Input ing Threshold vs. Logic upply Voltage 3. Input ing Threshold vs. upply Voltages = 1 V = T A = V T (V) W3, V TH (V) = V = V () Logic upply (V) ) r(on) rain-ource On-Resistance ( ) r(on) rain-ource On-Resistance ( 3 r (on) vs. V and Temperature 3 = 1 V, = = V V rain Voltage (V) r (on) vs. V and Power upply Voltage ( = ) Q (p) r (on) vs. V and Power upply Voltage 2 12 V 1 V 2 22 V T A = 2. V 12 V 12 V 1 V 1 2 V rain Voltage (V) 2 22 V ) r(on) rain-ource On-Resistance ( T A = 2 harge Injection vs. Analog Voltage = 1 V, = = V V V V rain Voltage (V) L = k pf 1 k pf pf 1 1 V ource Voltage (V) -233 Rev. F, -ep-99 FaxBack -9-

6 G1/3/ I (off) na na 1 na pa pa 1 pa Leakage urrent vs. Temperature = 1 V = = V V = V I (off) I (on) (pa) I, I Leakage urrent vs. Analog Voltage I (off), I (off) I (on) = 1 V, = = V, T A = 2 For I (off), V = For I (off), V =.1 pa Temperature ( ) 1 1 V or V rain or ource Voltage (V) n n upply urrent vs. Temperature = 1 V, = = V I+ I I L ing Time vs. Temperature* = 1 V, =, VL = V t ON t OFF I+, I, I L (A) 1 n p t ON, t OFF (ns) 1 9 V = V V = V V = V. p I L V = V I 3 1 p T A Temperature ( ) T A Temperature ( ) ing Time vs. Power upply Voltage* 3 ing Time vs. Positive upply Voltage* 1 1 V = V 2 2 V V = V t ON, t OFF (ns) 1 V = V V = V V = V t ON, t OFF (ns) V VL = V t ON t OFF 3 t ON t OFF , Positive and Negative upplies (V) *Refer to Figure 2 for test conditions. Positive upply (V) FaxBack Rev. F, -ep-99

7 G1/3/ V Level hift/ rive FIGURE 1. is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. + V +1 V Logic Input 3 V % t r < ns t f < ns V Input* V 9% t OFF R L 1 k L 3 pf Output Input* V t ON 9% L (includes fixture and stray capacitance) R O = V R L + r (on) *V = V for t ON, V = V for t OFF Note: Logic input waveform is inverted for switches that have the opposite logic sense control FIGURE 2. ing Time V 1 V 2 + V +1 V R L1 L1 1 Logic Input Output 3 V V 1 1 V 2 2 % 9% 9% R L2 L2 Output t t L (includes fixture and stray capacitance) FIGURE 3. Break-Before-Make -233 Rev. F, -ep-99 FaxBack -9-

8 G1/3/ + V +1 V R g V g 3 V L nf On Off On Q = x L FIGURE. harge Injection + V +1 V V R g = V, 2. V R L V + V +1 V R g = V, 2. V R L Off Isolation = log V = RF bypass = RF bypass FIGURE. Off Isolation FIGURE. Insertion Loss + V +1 V + V +1 V V R g = Meter R L. V, 2. V HP192A Impedance Analyzer or Equivalent f = 1 MHz X TALK Isolation = log = RF bypass V FIGURE. rosstalk FIGURE. apacitances FaxBack Rev. F, -ep-99

9 G1/3/ + V +1 V + V +1 V ource 1 Left Right Left e in e out Left ource 2 Right 2 Right TTL Integrate/ Reset 2 TTL hannel elect 2 lope elect 2 2 FIGURE 9. tereo ource elector FIGURE.ual lope Integrator ual lope Integrators: + V +1 V The is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor 1 or 2. Another one selects e in or discharges the capacitor in preparation for the next integration cycle Band-Pass ed apacitor Filter: e in 2 ingle-pole double-throw switches are a common element for switched capacitor networks and filters. The fast switching times and low leakage of the allow for higher clock rates and consequently higher filter operating frequencies. lock 2 + e out FIGURE 11.Band-Pass ed apacitor Filter -233 Rev. F, -ep-99 FaxBack -9-9

10 G1/3/ Peak etector: A 3 acting as a comparator provides the logic drive for operating W 1. The output of A 2 is fed back to A 3 and compared to the analog input e in. If e in > e out the output of A 3 is high keeping W 1 closed. This allows 1 to charge up to the analog input voltage. When e in goes below e out A 3 goes negative, turning W 1 off. The system will therefore store the most positive analog input experienced. Reset W 2 e in A1 + W 1 R 1 + A 2 e out + A 3 G1 1 FIGURE 12.Positive Peak etector FaxBack Rev. F, -ep-99

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