Design-Kits, Libraries & IPs



Similar documents
STMicroelectronics. Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI. SOI Processes 130nm, 65nm. SiGe 130nm

How To Integrate 3D-Ic With A Multi Layer 3D Chip

Procedure to get a design kit

3D-IC Integration Developments & Cooperations for servicing

University of Texas at Dallas. Department of Electrical Engineering. EEDG Application Specific Integrated Circuit Design

Quality. Stages. Alun D. Jones

1. Submission Rules. 2. Verification tools. 3. Frequent errors

Digital IC Design Flow

IL2225 Physical Design

System-on. on-chip Design Flow. Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems.

Designing a System-on-Chip (SoC) with an ARM Cortex -M Processor

INF4420 Introduction

EEC 118 Lecture #17: Implementation Strategies, Manufacturability, and Testing

CADENCE LAYOUT TUTORIAL

MEMS Processes from CMP

Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design

Agenda. Michele Taliercio, Il circuito Integrato, Novembre 2001

Digital Systems Design! Lecture 1 - Introduction!!

A Mixed-Signal System-on-Chip Audio Decoder Design for Education

State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop

How To Design A Chip Layout

ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path

StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs

Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic

Complete ASIC & COT Solutions

7a. System-on-chip design and prototyping platforms

ESP-CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation

SR. SIGNAL INTEGRITY ENGINEER

Serial port interface for microcontroller embedded into integrated power meter

EEC 119B Spring 2014 Final Project: System-On-Chip Module

Unlimited Product Licensing Cost-Effectively Eliminate Design Bottlenecks. Dr Ivan Pesic

PowerPlay Power Analysis & Optimization Technology

The GoldenGate Working Group

Contents. Overview Memory Compilers Selection Guide

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis

Virtuoso Analog Design Environment Family Advanced design simulation for fast and accurate verification

on-chip and Embedded Software Perspectives and Needs

Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com

Route Power 10 Connect Powerpin 10.1 Route Special Route 10.2 Net(s): VSS VDD

Ingar Fredriksen AVR Applications Manager. Tromsø August 12, 2005

CILOMAG & SPIN Projects. CMOS / Magnetic Integration

ATMEL FPGA 3rd User Group Workshop. 2010, 3rd June Christophe POURRIER

International Journal of Electronics and Computer Science Engineering 1482

Implementation Details

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures

Altera Error Message Register Unloader IP Core User Guide

Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX

Simulation and Design Route Development for ADEPT-SiP

Streamlining the creation of high-speed interconnect on digital PCBs

CMP is a service organization. prototyping and low volume production. carrousel. >>>>>>>>>> Flash info >>>>>>>>>> Design A Design B Your design

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis

E158 Intro to CMOS VLSI Design. Alarm Clock

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

EE411: Introduction to VLSI Design Course Syllabus

IBIS for SSO Analysis

ECE 410: VLSI Design Course Introduction

Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai Jens Onno Krah

Introduction to Digital System Design

EEM870 Embedded System and Experiment Lecture 1: SoC Design Overview

An Advanced Behavioral Buffer Model With Over-Clocking Solution. Yingxin Sun, Joy Li, Joshua Luo IBIS Summit Santa Clara, CA Jan.

Chapter 13: Verification

Power Reduction Techniques in the SoC Clock Network. Clock Power

Status of CBM-XYTER Development

System on Chip Design. Michael Nydegger

Sequential 4-bit Adder Design Report

Advanced VLSI Design CMOS Processing Technology

Impact of Signal Integrity on System-On-Chip Design Methodologies

Quartus II Software and Device Support Release Notes Version 15.0

SDN and Streamlining the Plumbing. Nick McKeown Stanford University

數 位 積 體 電 路 Digital Integrated Circuits

DIGITAL DESIGN FLOW OPTIONS

UTBB-FDSOI 28nm : RF Ultra Low Power technology for IoT

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow

Low Power AMD Athlon 64 and AMD Opteron Processors

3. On the top menu bar, click on File > New > Project as shown in Fig. 2 below: Figure 2 Window for Orcad Capture CIS

Understanding DO-254 Compliance for the Verification of Airborne Digital Hardware

ECE 5745 Complex Digital ASIC Design Course Overview

High-Level Synthesis for FPGA Designs

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition

Digital Integrated Circuit (IC) Layout and Design

Printed Circuit Board Design with HDL Designer

EDA Vendor Support. Table 1 Alliance Program EDA Vendors. Actel s Alliance Partners. Company Contact Address

A NEAR FIELD INJECTION MODEL FOR SUSCEPTIBILITY PREDICTION IN INTEGRATED CIRCUITS

IMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR

Training Course of SOC Encounter

DEVICE DRIVERS AND TERRUPTS SERVICE MECHANISM Lesson-14: Device types, Physical and Virtual device functions

Space product assurance

SABRE Lite Development Kit

Wireless Security Camera

Embed-It! Integrator Online Release E March 2011

Table 1. The relationship between courses and EDA tools (P: PC, M: MAC, U:Unix Workstation, T: Engineering Technology only).

High-Frequency Integrated Circuits

Transcription:

Design-Kits, Libraries & IPs

Supported CAD tools Design-kits overview Digital, Analog, and RF Libraries IPs Supported CAD tools Design-kits overview ST 65nm Tanner PDK Standard cell Libraries IPs

austriamicrosystems 0.35µm CMOS 0.35µm SiGe 0.35µm HV-CMOS 0.18µm CMOS 0.18µm HV-CMOS

austriamicrosystems Supported CAD Tools Schematic & Design Entry Electrical Simulation Digital Simulation Logic Synthesis Layout & Verification P&R Cadence Composer (CDS) Spectre (CDS) Hspice Ultrasim NC-Sim, AMS-Designer Verilog BuildGates Virtuoso-XL Diva Assura SOC Encounter Silicon Ensemble Mentor Synopsys DA (MGC) Eldo (MGC) ModelSim Leonardo IC / Calibre IC-Route Design Compiler Hspice VSS / VCS Design Compiler StarRCXT Astro / ICC Tanner SimulationModels S-Edit TSpice TSpice --- L-Edit DRC Pspice (CDS) Saber (Synopsys) ADS (Agilent) Smash (Dolphin) SmartSpice (Silvaco) SPR

AMS Design-Kits Current distributions : Cadence (SUN / Linux) Mentor (SUN / Linux) Tanner (MS-Windows) CDB OA - - C35 (0.35µm CMOS) 3.80 4.1 3.70 7.3 S35 (0.35µm SiGe) 3.80 4.1 3.70 - H35 (0.35µm HV-CMOS) 3.82 4.1 3.71 - C18 (0.18µm CMOS) 3.78 4.01 - - H18 (0.18µm HV-CMOS) 3.78 4.01 - -

AMS Libraries LV Digital standard cells and IO Libraries : CORELIB : General purpose digital library CORELIB_3B : Same as CORELIB with 3 busses (VDD, VSS, GND) IOLIB : IO pads (input, output, bidir). 3.3V and 5V available IOLIBC_3B : Core limited digital IO Libraries Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. HV Digital standard cells and IO Libraries : CORELIB_HV : CORELIB for high voltage. IOLIB_HV : High Voltage digital IO pads library Analog standard cells Libraries : IOLIB_ANA : Analog IO pads library IOLIBC_ANA_3B : Core limited Analog IO pads library IOLIB_ANA_HV : High Voltage Analog IO pads library A_CELLS : Analog Library RF standard IO cells Libraries : SPIRAL : Library with characterized Inductors RF_PADS : RF IO pads library

AMS IP Blocks IP blocks available from CMP free of charge to Univ. & Research (0.35µ CMOS) Single & Dual Port RAMS configurations: Single Port RAM Dual Port RAM Diffusion ROM Bits Words 8 9 12 16 32 128 SP SP SP SP SP 256 DP SP / DP SP 512 SP SP 600 SP 1024 SP / DP SP / DP 2048 SP SP / DP SP 4098 DP

STMicroelectronics HCMOS9 (130nm CMOS) HCMOS9-SOI (130nm CMOS-SOI) BiCMOS9-MW (130nm CMOS) CMOS065 (65nm CMOS) CMOS065-SOI (65nm CMOS-SOI) CMOS040 (40nm CMOS) CMOS028 (28nm CMOS) New 28FDSOI (28nm FD-SOI)

STMicroelectronics supported CAD Tools IC Electrical Simulation Verification Parasitics Extraction P&R CDB 5.1.41 OA 6.1.4 Spectre (CDS) Eldo (MGC) Hspice (SNPS) ADS (Agilent) Calibre (MGC) StarRCXT (SNPS) Calibre (MGC) QRC (CDS) Encounter (CDS) ICC (SNPS) HCMOS9 x x x x x x x x HCMOS9- SOI x x x x x x x - - BiCMOS9- MW x x x x x x x x x CMOS065 x x x x x x x x x x x CMOS065- SOI x x x x x x CMOS040 x x x x x x CMOS028 x x x x x x x CMOS028 x Q2 2013 x x Q2 2013 x x Q2 2013 x x

STMicroelectronics Design-Kits Current distributions : Cadence (SUN/ HP / Linux) HCMOS9 9.2 HCMOS9-SOI 10.0 BICMOS9-MW 2.4a Tanner (MS-Windows) CMOS065 5.3.4 / 5.3.6 V3 CMOS065-SOI 4.2 CMOS040 2.1 / 2.3 CMOS028 4.2 28FDSOI 2.0a RF option available for HCMOS9 & CMOS065 design kits.

ST 65nm Tanner PDK Full-Custom design environment (Frontend + Backend) All basic devices have been ported from the ST environment to the Tanner Tools. Frontend : - Schematic Capture using S-Edit. - Spice simulation using TSpice. Backend : - Layout Edition using L-Edit. - Parametic layout cells (T-Cells) - Verification using L-Edit/DRC and LVS. New To be done : - Standard-cells (schematics and abstracts) - Qualifying the HiPer Design Suite

Standard Cells Libraries from STMicroelectronics CORE cells Libraries : CORE : General purpose core libraries CORX : Complementary core libraries (complex gates) CLOCK : Buffer cells and the same for clock tree synthesis PR : Place and route filler cells and the same. DP : Datapath leaf cells libraries HD : High density core libraries IO cells Libraries : 1.8V, 2.5V, 3.3V IO pads: 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog Staggered IO pads Flip-Chip pads Level Shifters, and compensation cells On request: LVDS Pads DLL, PLL Memories SPRAM / DPRAM / ROM available on request, free of charge (1-2 weeks delay) on request

IP Blocks Available from STMicroelectronics ARM 946EJ-S : HCMOS9 130nm CMOS IP core Simulation models Abstract view for P&R Timing Files for STA and backannotated simulation Available under NDA ARM 926EJ-S : CMOS065 65nm CMOS IP core Simulation models Abstract view for P&R Timing Files for STA and backannotated simulation Available under NDA + Access to all available ARM cores in 65nm.

Design-Kit Support at CMP Management and support of the DK distribution and updates. Development, support and maintenance of design-kits. Tutorials on some design flows. Two CMP engineers working partly at ST to solve all kind of support with ST design-kits and memory blocks generation.

2026 © DocPlayer.net Privacy Policy | Terms of Service | Feedback  | Do Not Sell My Personal Information