1. Submission Rules. 2. Verification tools. 3. Frequent errors
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1 Design Submission 1. Submission Rules 2. Verification tools 3. Frequent errors
2 Design submission rules 1. Send the submission form in the same time as the circuit database 2. The GDSII file must have a.gds or.gds.gz extension 3. Provide a.info text file containing : designer and institution names, , phone number 4. Give in the.info the GDSII check sum of the database sent 5. The topcell name must be identical to the GDSII file : TOP_CELL.gds 6. Rename the topcell for each new version : TOP_CELL_V2 7. Do not use the standard cell names for your own cells Rename yours into MY_INV0, MY_ICP
3 Verification tools DRC verification tools DIVA and ASSURA, on cadence DIVA and ASSURA work on the database Mostly used for interactive verification Calibre, on Mentor Calibre works on the GDSII file Mostly used for final verifications since it is the «sign-off» tools for the foundries (austriamicrosystems, STMicroelectronics) ote: Techno files are included in the Design Kits distributed by CMP
4 Compatibility between DIVA and CALIBRE With DIVA and Assura, the errors appear on Cadence on a blinking Marker layer Calibre generates an ASCII DRC result file. The RVE interface can be used on Cadence. CMP provide a file (generated from the ASCII file) which enables to see the errors with Cadence on the same layer as DIVA.
5 Frequent errors Antenna Generated layers Path Wide-Metal Off-grid Resistors L/W ratio Metal density Logo VIA / CONT Substrate / Wells connections Metal Slots Hot NTUB Floating Gates
6 Antenna errors Problem during the fabrication Connection surface There is a ratio to be respected: Gates surface G D S
7 Antenna correction (1) Antenna error correction: 1 st solution Make a bridge with a upper metal layer MET1 / VIA / MET2 / VIA / MET1
8 Antenna correction (2) Antenna error correction: 2 nd solution Place a minimum diode N+diff / Substrate near the transistor gate
9 Generated layers 0.35 µm CMOS FIMP, NLDD et NLDD50 La couche FIMP est générée à partir de la couche NTUB La couche NLDD est générée à partir de la couche NPLUS La couche NLDD50 est générée à partir de la couche NPLUS et MIDOX
10 WIDE-METAL MET to WIDE_MET Spacing > 10 µm D D
11 Errors on PATH 45 PATH introduce off grid errors PATH length: even number of grid pitch
12 Frequent errors Off grid : µm grid in 0.35 µm Square L / W: the ratio should be 5 for resistors Metal / Poly density Polarization contact Must be placed every 50 µm NWell polarized to VDD PWell (substrate) polarized to GND
13 Logo CMP delete non standard logos (resin and metal ) Make a simple logo with 1 VIA by polygon
14 VIA / CONT Size VIA : Imposed in 0.35 µm CONT : Imposed in 0.35 µm MET1 Poly1 Oxide Diffusion Substrate
15 Substrate / Wells connections Vdd R Recommended
16 Metal Slots Make openings in the wide metal Increase the metal and resin adherence Decrease the electro migration effects W > 10 µ Staggered metal slot W < 10 µ W > 10 µ Divide in smaller paths
17 Hot NTUB / Floating Gates Add Vdd and Gnd labels on all the pads Using PIN pd layer At the topcell level With this syntax: vdd3, gnd4
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