EDA Vendor Support. Table 1 Alliance Program EDA Vendors. Actel s Alliance Partners. Company Contact Address

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1 EDA Vendor Support This document describes the EDA environments that supports. This document also covers each of the -supported vendors. Within each vendor s tool set the features will be described that are supported by. Also listed are the software and computer requirements for integrating Designer Series with the EDA front-end tools. Table 1 Alliance Program EDA Vendors s Alliance Partners s Alliance program was established to assist EDA vendors in providing support for FPGAs. The Alliance program provides early technical information on new releases to all partners so they can offer timely support. Table 1 lists the complete set of EDA vendors that support the design of FPGAs. 2 Company Contact Address Acugen J. W. Brooks (603) Amherst St., Suite 391, Nashua, NH Aldec Stanley Hyduke (805) Old Conejo Road, Suite 111 Newbury Park, CA Cadence Itzhak Shapira (408) Seely Road, Bldg. 6, San Jose, CA Compass John Goldsworthy 1865 Lundy Ave., San Jose, CA (408) ext Escalade Mark Miller (408) Augustine Dr., 2nd Floor, Santa Clara, CA Exemplar Logic Mary Murphy (510) Atlantic Ave., Suite 105, Alameda, CA Intergraph Will Wong (415) East Evelyn Avenue, Mountain View, CA Isdata Ralph Remme Daimlerstr. 51, Karlsruhe, D-76185, Germany IST Gabriele Saucier Europole, 4 Place Robert Schuman Grenoble Cedex 1, France Logic Modeling Marnie McCollow (503) N.W. Gibbs Drive, Beaverton, OR (Synopsys) Logical Devices David Motarjemi (305) N.W. 65th Place, Ft. Lauderdale, FL Mentor Graphics Sam Picken (503) S.W. Boeckman Road, Wilsonville, OR Minc Wayne Merrill (719) Earl Drive, Colorado Springs, CO OrCAD Troy Scott (503) S.W. Nimbus, Beaverton, OR Quad Design Hector Lai (805) Del Norte Road, Camarillo, CA Simucad John Williamson (415) Alvarado-Niles Rd., Suite 744, Union City, CA Synario Design Dave Kohlmeiyer (206) Willows Road N.E., Redmond, WA Automation Synopsys Lynn Fiance (415) East Middlefield Road, Mountain View, CA Synplicity Alisa Yaffa (415) Fairchild Dr., Suite 115, Mountain View, CA Teradyne Bill Loring (617) Lincoln St., M/S L50, Boston, MA Veda Design Automation (formerly Genrad) Rastgow Shale (408) Mission College Blvd., Suite 259 Santa Clara, CA Viewlogic Dave Orecchio (508) Boston Post Road, Marlboro, MA Zuken Dwight Dagenais (408) Freedom Circle, Suite 1100, Santa Clara, CA April Corporation

2 Designer Series for Cadence Design Systems EDA Tools Concept RapidSIM Concept Verilog, RapidSIM Synergy Leapfrog Designer Series Development System ACTgen Pin Editor ChipEdit Compile Layout Standard/DirectTime ACTmap DirectTime Editor DT Analyzer & Back Annotation Activator 2 Activator 2s Data I/O Figure 1 The Cadence EDA Environment The Designer Series Development System for the Cadence Design Systems environment (see Figure 1) allows FPGAs with from 1,000 to 30,000 gates to be designed with Cadence s Concept (Logic Workbench) or Composer schematic capture tools. Designer Series provides libraries that support the design of ACT 1, the Integrator Series, and the Accelerator Series families of FPGAs. In addition, Designer Series provides ACTmap VHDL Synthesis (a complete VHDL synthesis and logic optimization tool) and ACTgen Macro Builder, which creates complex logic functions to match user-specified parameters. For Cadence, Designer Series supports the following combinations of schematic capture and simulation: Composer and Verilog XL Concept and RapidSIM Concept and Verilog These design flows allow schematics to be created using Composer or Concept. Designer Series products include netlisters that convert Composer or Concept schematics into a netlist format that Designer Series can accept. The netlist is then simulated with unit delays to verify the design functionally before running place and route. After place and route, actual module and net delays are backannotated to the netlist for timing simulation. s DirectTime Analyzer is used to perform static timing analysis on a design identifying critical path delays and performance deltas relative to design specifications. Once the implementation has met all timing requirements, the design can be programmed into an FPGA. s optional DirectTime Layout feature can be added to the basic Designer Series Cadence interface. DirectTime Layout supports specification-driven design. With DirectTime Layout, the system clock frequency or delay constraints for individual signals can be entered. After s standard place-and-route algorithm is executed, the results are shown in the DirectTime Analyzer. DirectTime Analyzer displays a comparison between required versus actual delays. DirectTime Layout can typically improve design performance by an amount equivalent to the next fastest speed grade. It makes performance-runtime trade-offs during placement and routing to achieve the requested timing. 2-18

3 EDA Vendor Support If the results of standard layout are substantially slower than the required timing, more aggressive measures are needed. The designer has the option of moving to a faster-speed-grade FPGA or even to a faster family. DirectTime Analyzer makes these decisions easy by clearly showing whether the target performance is reached and showing the distance between target and achieved when target is missed. There are many high-level design solutions that support in the Cadence environment. Cadence s Synergy and PIC Designer products as well as Synopsys s Design and FPGA Compilers all work within the Cadence environment. Synthesized blocks in any of these synthesis tools can be combined with schematics to support mixed-level design definition. Cadence provides libraries for the PIC Designer and Synergy synthesis products. s Synopsys synthesis libraries can be added to the Designer Series Development System to support Synopsys synthesis in the Cadence environment. also makes available Verilog and VITAL VHDL libraries so that designs captured in these languages can be simulated directly with Verilog XL or Leapfrog. The Designer Series Development System for Cadence provides a tight link between Cadence s suite of design capture and analysis tools and s FPGA implementation software. The integration of Designer Series with the Cadence tools provides a design environment that delivers high-performance, high-capacity FPGA solutions quickly. Combining the architecture with powerful place-and-route software provides short turnaround time for ECNs. Designer Series makes it easy to include custom logic in any product. Sun SPARC or HP 700 Hardware Requirements 64 MB RAM 125 MB DISK (executables), 5 MB DISK (per design) CD-ROM drive Software Requirements Sun OS or later, Solaris 5.3 or later, OR HP-UX 9.03 or later Version 9404 or later

4 Designer Series for Mentor Graphics EDA Tools Design Architect QuickSim II Autologic QuickVHDL Designer Series Development System ACTgen Pin Editor ChipEdit Compile Layout Standard/DirectTime ACTmap DirectTime Editor DT Analyzer & Back Annotation Activator 2 Activator 2s Data I/O Figure 2 The Mentor Graphics EDA Environment The Designer Series Development System for the Mentor Graphics environment (see Figure 2) allows FPGAs with from 1,000 to 30,000 gates to be designed with Mentor Graphics Design Architect. Designer Series provides libraries that support the design of ACT 1, the Integrator Series, and the Accelerator Series families of FPGAs. In addition, Designer Series provides ACTmap VHDL Synthesis (a complete VHDL synthesis and logic optimization tool) and ACTgen Macro Builder, which creates complex logic functions to match user-specified parameters. The design flow for Mentor Graphics allows schematics to be entered using Design Architect. Designer Series products include netlisters that convert Design Architect schematics into EDIF, which Designer Series can accept. The netlist is then simulated with unit delays to verify the design functionally before running place and route. After place and route, actual module and net delays can be backannotated to the netlist for timing simulation. s DirectTime Analyzer can be used to perform static timing analysis on a design identifying critical path delays and performance deltas relative to design specifications. Once the implementation has met all timing requirements, the design can be programmed into an FPGA. s optional DirectTime Layout feature can be added to the basic Designer Series Mentor Graphics interface. DirectTime Layout supports specification-driven design. With DirectTime Layout, the system clock frequency and delay constraints for individual signals can be entered. After s standard place-and-route algorithm is executed, the results are shown in DirectTime Analyzer. DirectTime Analyzer displays a comparison between required versus actual delays. DirectTime Layout can typically improve design performance by an amount equivalent to the next fastest speed grade. It makes performance-runtime trade-offs during placement and routing to achieve the requested timing. If the results of standard layout are substantially slower than the required timing, more aggressive measures are needed. The designer has the option of moving to a faster-speed-grade FPGA or even to a faster family. DirectTime Analyzer makes these decisions easy by clearly showing whether the target performance is reached and showing the distance between target and achieved when target is missed. There are many high-level design solutions that support in the Mentor Graphics environment. Mentor Graphics Autologic and Autologic II products as well as Synopsys s Design and FPGA Compilers all work within the Mentor 2-20

5 EDA Vendor Support Graphics environment. Synthesized blocks in any of these synthesis tools can be combined with schematics to support mixed-level design definition. Mentor Graphics provides the libraries for Autologic synthesis products. s Synopsys synthesis libraries can be added to the Designer Series Development System to support Synopsys synthesis in the Mentor Graphics environment. also makes available Verilog and VITAL VHDL libraries so that designs captured in these languages can be simulated directly with QuickSim or QuickVHDL. The Designer Series Development System for Mentor Graphics provides a tight link between the Mentor Graphics suite of design capture and analysis tools and s FPGA implementation software. The integration of Designer Series with the Mentor Graphics tools provides a design environment that delivers high-performance, high-capacity FPGA solutions quickly. Combining the architecture with powerful place-and-route software provides short turnaround time for ECNs. Designer Series makes it easy to include custom logic in any product. Sun SPARC or HP 700 Hardware Requirements 64 MB RAM 125 MB DISK (executables), 5 MB DISK (per design) CD-ROM drive Software Requirements Sun OS or later, Solaris 5.3 or later, OR HP-UX 9.03 or later Version 8.2_5 or later (A.1 recommended)

6 Designer Series for Viewlogic EDA Tools PRO Series PRO Capture PRO Sim PowerView ViewDraw ViewSim ViewSyn SpeedWave Designer Series Development System ACTgen Pin Editor ChipEdit Compile Layout Standard/DirectTime ACTmap DirectTime Editor DT Analyzer & Back Annotation Activator 2 Activator 2s Data I/O Figure 3 The Viewlogic EDA Environment The Designer Series Development System for the Viewlogic environment (see Figure 3) allows FPGAs with from 1,000 to 30,000 gates to be designed with Viewlogic s Workview Office or PowerView tools. Designer Series provides libraries that support the design of ACT 1, the Integrator Series, and the Accelerator Series families of FPGAs. In addition, Designer Series provides ACTmap VHDL Synthesis (a complete VHDL synthesis and logic optimization tool) and ACTgen Macro Builder, which creates complex logic functions to match user-specified parameters. For Viewlogic, Designer Series supports the following workstation-product combinations: 486 and Pentium PCs: Workview Office HP 700 and Sun workstations: PowerView These design flows allow schematics to be created using PowerView on the workstations or Workview Office on the PC. The Designer Series products include netlisters that convert PowerView or Workview Office schematics into an EDIF netlist that Designer Series can accept. The netlist is then simulated with unit delays to verify the design functionally before running place and route. After place and route, actual module and net delays are backannotated to the netlist for timing simulation. s DirectTime Analyzer is used to perform static timing analysis on a design identifying critical path delays and performance deltas relative to design specifications. Once the implementation has met all timing requirements, the design can be programmed into an FPGA. s optional DirectTime Layout feature can be added to the basic Designer Series Viewlogic interface. DirectTime Layout supports specification-driven design. With DirectTime Layout, the system clock frequency and delay constraints for individual signals can be entered. After s standard place-and-route algorithm is executed, the results are shown in DirectTime Analyzer. DirectTime Analyzer displays a comparison between required versus actual delays. DirectTime Layout can typically improve design performance by an amount equivalent to the next fastest speed grade. It makes performance-runtime trade-offs during placement and routing to achieve the requested timing. If the results of standard layout are substantially slower than the required timing, more aggressive measures are needed. The designer has the option of moving to a faster-speed-grade FPGA or even to a faster family. DirectTime Analyzer makes these decisions easy by clearly showing whether the target 2-22

7 EDA Vendor Support performance is reached and showing the distance between target and achieved when target is missed. There are many high-level design solutions that support in the Viewlogic environment. Viewlogic s ViewSynthesis as well as Synopsys s Design and FPGA Compilers all work within the Viewlogic environment. Synthesized blocks in any of these synthesis tools can be combined with schematics to support mixed-level design definition. Viewlogic provides libraries for the ViewSynthesis product. s Synopsys synthesis libraries can be added to the Designer Series Development System to support Synopsys synthesis in the Viewlogic environments. also makes available Verilog and VITAL VHDL libraries so that designs captured in these languages can be simulated directly with Chronologic or Speedwave. The Designer Series Development System for Viewlogic provides a tight link between Viewlogic s suite of design capture and analysis tools and s FPGA implementation software. The integration of Designer Series with the Viewlogic tools provides a design environment that delivers high-performance, high-capacity FPGA solutions quickly. Combining the architecture with powerful place-and-route software provides short turnaround time for ECNs. Designer Series makes it easy to include custom logic in any product. 486 or Pentium PC Hardware Requirements VGA, EGA graphics card 32 MB RAM 60 MB virtual disk 70 MB DISK (executables), 5 MB DISK (per design) CD-ROM drive Software Requirements Windows 3.1 or later, Windows NT or later, Windows 95 PROSeries 6.1 or later Workview Office 7.1 or later Sun SPARC or HP 700 Hardware Requirements 64 MB RAM 125 MB DISK (executables), 5 MB DISK (per design) CD-ROM drive Software Requirements Sun OS or later, Solaris 5.3 or later, OR HP-UX 9.03 or later PowerView 5.3 or later

8 Designer Series for Synopsys EDA Tools Synopsys Verilog HDL/VHDL Synthesis Designer Series Development System ACTgen Pin Editor ChipEdit Compile Layout Standard/DirectTime ACTmap DirectTime Editor DT Analyzer & Back Annotation Activator 2 Activator 2s Data I/O Figure 4 The Synopsys EDA Environment The Synopsys libraries support synthesis of FPGAs from Verilog HDL or VHDL. (See Figure 4.) Support for synthesis, DesignWare, and VHDL System Simulator (VSS) is included. The Synopsys libraries provide a complete top-down design solution. FPGA designs can be compiled with either the Design Compiler or the FPGA Compiler, with the FPGA Compiler yielding more efficient, high-performance FPGA implementations. The combination of s fine-grain, routing-resource-rich architecture and Synopsys s powerful synthesis program delivers high-performance, high-capacity FPGAs. The Synopsys libraries allow designs to be efficiently mapped to the architecture, taking complete advantage of all possible logic module functions. Design implementation efficiency is enhanced by the DesignWare library, which contains -optimized adders, counters, multiplexers, registers, and so on. These logic elements all can be instantiated into a high-level design description. Adders, comparators, and subtracters can be inferred from arithmetic operators that are used in the behavioral description. Synopsys has included -specific optimization, such as sequential mapping, which takes full advantage of the multiplexer-based, flip-flop-oriented FPGA architecture. The combination of Synopsys s optimizations for FPGAs and the optimized DesignWare logic elements generates designs that are typically within 5 percent of what can be achieved by laborious handcrafting. Simulation of the design with its surrounding test bench can be accomplished by using VSS and s VHDL libraries for Synopsys or by using any Verilog simulator and the separately available Verilog libraries. Both the Verilog and VHDL simulation libraries support preroute functional simulation to verify the design s functionality and accurate postroute timing simulation with backannotated (using SDF) actual delays. Timing simulation can be performed with best-case, worst-case, or typical delays to account for variations in voltage, process, and temperature. This accurate timing simulation can identify areas in which timing error is causing a design to malfunction. The Synopsys libraries support many of the FPGA-specific architectural feature, such as ACT 3 s complex I/O cells, 1200XL s wide-decode feature, and 3200DX s quad-clock and embedded RAM features. Synopsys s support of architectural specialties allows designers to maximize FPGA performance 2-24

9 EDA Vendor Support and usefulness by synthesizing a design that includes high-speed FIFOs or dual-port RAMs in a 32200DX device, or by targeting the I/O flip-flops of the ACT 3 family to locate a high-speed counter right on a data bus. The DesignWare libraries provide a strong advantage in the design of FPGAs. provides a synthetic library in DesignWare, which includes commonly used functions such as accumulators, adders, comparators, counters, decoders, multiplexers, and registers up to 32 bits wide. Each logic function can be created with a designer-selected combination of control signals. By taking advantage of the synthetic library, the VHDL or Verilog code can be fine-tuned for optimal implementation. These libraries are based upon s ACTgen Macro Builder parameterized macro generator, which allows designers to achieve performance comparable to schematic-drawn macros. DesignWare elements can be instantiated into the code or inferred by the compilers, resulting in an extremely efficient design process. Sun SPARC or HP 700 Hardware Requirements 64 MB RAM 125 MB DISK (executables), 5 MB DISK (per design) CD-ROM drive Software Requirements Sun OS or later, Solaris 5.3 or later, OR HP-UX 9.03 or later Synopsys 3.2b or later

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