STMicroelectronics. Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI. SOI Processes 130nm, 65nm. SiGe 130nm

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1 STMicroelectronics Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI SOI Processes 130nm, 65nm SiGe 130nm

2 CMP Process Portfolio from ST Moore s Law 130nm CMOS : HCMOS9GP More than Moore 130nm SiGe : BICMOS9MW 65nm CMOS : CMOS065LPGP 130nm HV-CMOS : HCMOS9A 40nm CMOS : CMOS040LP 65nm SOI : CMOS065-SOI 28nm CMOS : CMOS028LP 130nm SOI : HCMOS9-SOI 28nm FDSOI : 28FDSOI

3 Feature Size 1300 x density integration 1/1000 x gate delay (from ns to ps) 1/1000 x power consumption (from µw/mhz to nw/mhz) AMS 0.8µ AMS 0.6µ AMS 0.35µ ST 0.25µ ST 0.18µ 1.2k gates/mm 2 3k gates/mm 2 18k gates/mm 2 35k gates/mm 2 80k gates/mm 2 ST 130nm 180k gates/mm 2 ST 90nm 400k gates/mm 2 ST 65nm 800k gates/mm 2 ST 40nm ST 28nm 1600k gates/mm at CMP 2013 at CMP

4 HCMOS9 Process From STMicroelectronics H9 C65 C40 C28 C65 SOI H9 SOI B9 MW STMicroelectronics CMOS 130nm HCMOS9

5 HCMOS9 Process Features H9 C65 C40 C28 C65 SOI H9 SOI B9 MW 130nm mixed A/D/RF CMOS SLP/6LM (triple Well) Gate length (130nm drawn). 6 Cu metal layers. Low k inter-level dielectric Power supply: 1.2 V Multiple Vt transistor offering (Low Leakage, High Speed) 6 levels Cu Metal (Cross View) Courtesy STMicroelectronics Threshold voltages : VTN = 500/380 mv, VTP = 480/390 mv Isat : 1.2 V : 535/680 ua/um; 1.2 V : 240/320 ua/um

6 CMOS065 Process From STMicroelectronics H9 C65 C40 C28 C65 SOI H9 SOI B9 MW STMicroelectronics 65nm CMOS CMOS065

7 CMOS065 CMOS 65nm Process Features H9 C65 C40 C28 C65 SOI H9 SOI B9 MW 65nm poly length Dual or triple Vt MOS transistors Dual or triple gate oxide Dedicated process flavors for high performance or low power Dual-damascene copper for interconnect Low-k (k = 2.9) dielectric 7 metal layers 0.20 micron metallization pitch Analog/RF capabilities 800 kgates/mm 2 Various power supplies supported: 2.5V, 1.8V, 1.2V, 1V Available at CMP since Q4 2006

8 CMOS065 Process From STMicroelectronics H9 C65 C40 C28 C65 SOI H9 SOI B9 MW STMicroelectronics 40nm CMOS CMOS040LP

9 40nm CMOS Process H9 C65 C40 C28 C65 SOI H9 SOI B9 MW CMOS040LP Process Features : Multiple library elements can be selected at the design level and used in the same design block, providing users of the platform with greater flexibility in optimizing performance and power consumption. Densities of up to 1600 Kgates / mm 2, supporting a core supply of 1.1V, with metal pitches of 0.14-micron, and 7 metal layers. Power reduction techniques include adaptive vdd, low vdd operation, power shutdown, low standby current, etc... Full range of 1.8V I/O cells. Extremely dense embedded memories: SRAM cells, with area sizes down to 0.25 square micron, at a supply voltage of 1.1V down to 0.9V

10 40nm CMOS Process H9 C65 C40 C28 C65 SOI H9 SOI B9 MW 5 circuits manufactured in 2012 MPW price : Euro/mm 2. (minimum price 1mm 2.) 3 MPW runs scheduled in 2013.

11 H9 C65 C40 C28 C65 SOI H9 SOI B9 MW STMicroelectronics 28nm CMOS CMOS28LP

12 28nm CMOS Process H9 C65 C40 C28 C65 SOI H9 SOI B9 MW 28nm poly length (32nm drawn) Dual or triple Vt MOS transistors Dual or triple gate oxide Low power process flavor Dual-damascene copper for interconnect Low-k (k = 2.9) dielectric 10 layer metal (optional 7 layer metal) 0.10 micron metallization pitch Various power supplies supported: 1.8V, 1.2V, 1V Embedded memory (Single port RAM / ROM / Double Port RAM )

13 28nm CMOS Process H9 C65 C40 C28 C65 SOI H9 SOI B9 MW 22 circuits manufactured in 2012 MPW price : Euro/mm 2. (minimum price 1mm 2.) 3 MPW runs scheduled in 2013.

14 28nm FDSOI Process Features (1/2) 28nm FDSOI, 10 Layers Metal, Triple Well Single IO oxide + Single core oxide. Double VT : 1.0V Low Vt transistors (LVT) + 1.0V super Regular Vt transistors (RVT) Low Leakage (high density) SRAM using LP core oxide IO supply voltage: 1.8 V using the IO oxide. 10 Cu metal layers : (6 thin + 2 medium + 2 thick) Ultra Low k inter-level dielectric 0.10µ metal pitch Process Options : MIM : Metal-Insulator-Metal Capacitance OTP (anti-fuse): Capacitance + Drift MOS transistor

15 28nm FDSOI Process Features (2/2) TRIPLE WELL (Deep N-WELL) allows isolating PWELL from the substrate. FULLY-DEPLETED SOI devices, with ULTRATHIN BOX and GROUND PLANE. COINTEGRATION with BULK devices. HIGH-K / METAL GATE for enhanced gate oxide capacitance and gate leakage reduction. Self-aligned SILICIDED DRAIN, SOURCE AND GATE: silicide is necessary to short N+ and P+ gates; Self-aligned Silicide on Source/Drain allows butting straps with only one minimum contact. POLY AND ACTIVE RESISTORS: Silicide protection over active areas, for ESD protection. Also to make poly resistors. CHEMICAL MECHANICAL POLISHING for enhanced planarization (on STI, Contacts, Metals and vias).

16 UTSOI compact model Model name: UTSOI Description: Ultra Thin Fully Depleted SOI MOSFET Model Model version: 1.12 (VerilogA code version 1.1.2a) Model format: fully integrated in Eldo (LEVEL 80), XA(-eldo), Hspice (LEVEL 76) Model Documentation provided in de design-kit. MOSFET Predefined corner cases Monte Carlo simulation case SOA models (Safe Operating Areas) Simulators versions to use: Eldo: ams 11.2 XA-eldo: f sp1-eng2 Hspice: f sp1-eng1 Hspice simulator might need additional UTSOI free License (ask Synopsys)

17 DRC checks increasing with process feature size Process 0.35um CMOS 130nm CMOS 90 nm CMOS 65 nm CMOS 40 nm CMOS 28nm CMOS 28nm FDSOI Nbr. of DRC RuleChecks # DRC Rule Checks +13% C35B4 130nm CMOS 90nm CMOS 65nm CMOS 40n CMOS 28nm CMOS 28nm FDSOI

18 28nm FDSOI Standard Cells Libraries CORE cells Libraries : CORE_LL : Low Power LVT CORE_LR : Low Power RVT CLOCK (LL and LR): Buffer cells and the same for clock tree synthesis PR : Place and route filler cells. IO cells Libraries : Digital Analog Flip-Chip bumps ESD Memories SPRAM / DPRAM / ROM available on request

19 Migrating from 28nm CMOS bulk to 28nm FDSOI No disruptive process, no disruptive design Migrating from 28nm CMOS bulk to 28nm FDSOI is seamless. Same layer numbers and names, allow to load a bulk design in a FDSOI design environment. Common design-rules platform (ISDA alliance design-rules) Bulk devices could be co-integrated with FDSOI devices

20 Customers accessing to 28nm CMOS (2/2) Customers using 28nm CMOS can migrate easily to the 28nm FDSOI 77 Users from 23 countries

21 28FDSOI MPW runs MPW price is Euro/mm 2. 3 MPW runs scheduled in 2013.

22 H9 C65 C40 C28 C65 SOI H9 SOI B9MW BiCMOS9MW Process 130nm SiGe:C BiCMOS process For millimiter wave, wireless, optical communications

23 BICMOS9MW Process Features H9 C65 C40 C28 C65 SOI H9 SOI B9MW BICMOS9MW technology is using 0.13µm HCMOS9 as base process. Address millimeterwave applications (frequencies up to 77GHz for automotive radar), wireless communication (frequencies around 60GHz for WLAN) and optical communications systems driving data rates up 80Gbit/s. SiGe-C bipolar transistor (ft around 230GHz) Process Features : CMOS devices for 1.2V applications. 2.5V Capable I/O's. A high performance NPN bipolar transistor. A medium voltage NPN bipolar transistor. Shallow trench isolation (STI), triple well (NISO), twin-tub, single poly, for CMOS core process. Deep trench isolation (DTI) combined with STI and SiGe-C epi base for NPN transistors Optional Dual Vt Back-end with 6 metal layers. Damascene Copper for metal 1 to last metal. Thin metal layers : metal 1 to 3 Thick metal layers : Metal4, Metal5 and Metal6. MIM capacitors

24 BICMOS9MW MPW runs H9 C65 C40 C28 C65 SOI H9 SOI B9MW 19 circuits manufactured in 2012 MPW price is 3500 Euro/mm 2. (4500 Euro/mm 2 for industrial users) 4 MPW runs scheduled in 2013.

25 H9 C65 C40 C28 C65 SOI H9 SOI B9 MW SOI processes

26 65nm CMOS SOI H9 C65 C40 C28 C65 SOI H9 SOI B9 MW CMOS065LP-SOI Process Features: - Partially Depleted SOI on High Resistivity Substrate - Triple-VT 1.2V transistors, with both floating body and Body-contacted versions - 1 thick oxide for either 1.8V or 2.5V IOs - 6 levels of metal (last metal is thick) - RF-MOS, RF-PADS, varactors, inductors... - MPW runs common to every CMOS065 bulk (3 MPW runs in 2012)

27 65nm CMOS SOI H9 C65 C40 C28 C65 SOI H9 SOI B9 MW MPW price is 9500 Euro/mm 2. 4 MPW runs scheduled in 2013.

28 130nm 130nm CMOS SOI H9 C65 C40 C28 C65 SOI H9 SOI B9 MW HCMOS9-SOI Process Features: - 1 thick oxide for 2.5V power supply - 6 metal layers - RF-MOS, RF-PADS, varactors, inductors... - MPW runs are common to every HCMOS9 bulk (4 MPW runs in 2013)

29 130nm 130nm CMOS SOI H9 C65 C40 C28 C65 SOI H9 SOI B9 MW 6 circuits manufactured in 2012 MPW price is 4000 Euro/mm 2. 4 MPW runs scheduled in 2013.

30 Conclusion Excellent Partnership CMP / STMicroelectronics. Efficient Technical Support. 65nm number of circuits continuing increasing 28nm CMOS & FDSOI rapidly adopted.