An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis

Transcription

1 An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis Oliver Schrape 1, Frank Winkler 2, Steffen Zeidler 1, Markus Petri 1, Eckhard Grass 1, Ulrich Jagdhold 1 International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2010) 1 2 Grenoble, France 10 th September 2010 HUB Institut für Informatik Rudower Chaussee Berlin

2 Outline Motivation Phase-Locked Loops Approaches Structure of the proposed ADPLL Chip Description Control Unit (CU) Digitally Controlled Oscillator (DCO) Frequency Divider Chip Layout Comparison Measurement Results 10th Sep. 10 2

3 Motivation How to get fast clocks in a circuitry? Some problems: Frequency limit of IO pads Solution: PLL (Phase-Locked Loop) EMI problems Clock skew of extern generated clocks Environmental effects 10th Sep. 10 3

4 PLL Traditional Approach PLL : Phase-Locked Loop Components Phase Frequency Detector (PFD), Loop Filter, Voltage Controlled Oscillator (VCO), Frequency Divider Advantages High resolution Low jitter Low phase noise Disadvantages Development time (costly) Process dependency 10th Sep. 10 4

5 PLL Digital Approach ADPLL : All-Digital Phase-Locked Loop Components: PFD, Control Unit, Digitally Controlled Oscillator (DCO), Frequency Divider Advantages Shorter development time Fast lock-in phase More adaptable to other circuit technologies Disadvantages Accuracy Large jitter Noisy 10th Sep. 10 5

6 ADPLL Fundamental Functionality Functionality (simplified) 1. Compare phases of reference and feedback clock 2. Increase or decrease the control word w 3. Divide generated clock by (M,S) 10th Sep. 10 6

7 Control Algorithms (1) linear / binary ADPLL is initialized with the mean value of valid DCO frequencies Additional counter allows an adjustment every x reference cycle CU evaluates up/down signals of the PFD Advantage: Few resources Low complexity Complexity: flag_u flag_d pwidth Control Unit OSC cnt1 + cnt2 Kp Kd + Ki cntx lin./bin. PID/PID2 w Disadvantage: Long lock-in phase 10th Sep. 10 7

8 Control Algorithms (2) PID Controllers Using a local ring oscillator to sample phase differences Additional counters measure the phase error Advantage: Short lock-in phase Disadvantage: Many logic resources flag_u flag_d pwidth Control Unit OSC cnt1 + cnt2 Kp Kd + Ki cntx lin./bin. PID/PID2 w General PID Controller: Innovation, smoothing with: 10th Sep. 10 8

9 Control Algorithms Matlab Model Simulation 250 Frequency Histogram Frequency Histogram 2 ADPLL Frequencies ADPLL Frequencies PID smoothed PID Count Count f [GHz] f [GHz] f [GHz] f [GHz] Reference Periods Reference Periods Algorithm Area [mm²] Power [µw] Lock Time [cycles] (non-)linear more than 1000 (smoothed) PID < 50 10th Sep. 10 9

10 Digitally Controlled Oscillator Structure Problem Frequency range vs. resolution Innovation Combining of three different approaches Wide frequency range with high resolution 10th Sep

11 Digitally Controlled Oscillator Structure Coarse-Tuning stage Multiplexer structures (one-hot-coded) [WASET 08] Resolution: > 300 ps 10th Sep

12 Digitally Controlled Oscillator Structure Coarse-Tuning stage Multiplexer structures (one-hot-coded) [WASET 08] Resolution: > 300 ps Fine-Tuning stage Bus keeper components (permutation) [IAPCS 2006] Resolution: 40 ps 10th Sep

13 Digitally Controlled Oscillator Structure Coarse-Tuning stage Multiplexer structures (one-hot-coded) [WASET 08] Resolution: > 300 ps Fine-Tuning stage Bus keeper components (permutation) [IAPCS 2006] Resolution: 40 ps Fine-Fine-Tuning stage Parallel connected tri-states (n:m code) [ECCTD 01] Resolution: < 5 ps 10th Sep

14 Digitally Controlled Oscillator Properties Requires only 46 logic gates (37, +9 additional inverter/buffer) Resolution < 1 ps Linearized steps: 5-25 ps Range: 250 MHz 1.3 GHz Post Layout Simulation with parasitic RC: clk_dco = 1.27 GHz, Temp: 125 C, VDD = 2.25 V 10th Sep

15 Frequency Divider Contains optional 2:1 prescaler and dual modulus (4/5) divider Swallow Counter switches dual modulus divider Programmable over SPI interface 10th Sep

16 Layout 3 power domains 1.6 mm x 1.6 mm size Macro blocks: DCO and LVDS interface Test board 1.6 mm x 1.6 mm 10th Sep

17 Properties Comparison Performance Parameter Proposed ADPLL Process 0.25 µm BiCMOS [ICSS 2003] [ECCTD 01] [NCETET 08] 0.35 µm CMOS 0.35 µm CMOS 0.18 µm CMOS Core Area 0.81 mm mm mm mm 2 Gates (DCO) 46 > Pwr. Dissip. < 50 mw (@ 800 MHz) 100 mw (@ 500 MHz) mw (-) Min. Freq. 250 MHz 45 MHz 170 MHz 0.1 MHz Max. Freq. 1.3 GHz 510 MHz 360 MHz 282 MHz Lock-in Time < 70 cycles < 46 cycles ~ 60 cycles < 5 cycles Resolution < 25 ps < 5 ps < 55 ps -- 10th Sep

18 Measurement Linear search algorithm, PLL locks at 560 MHz 10th Sep

19 Measurement Simple Multiplexer Paths 10th Sep

20 Conclusion Done: ADPLL with a wide frequency range and high resolution Combination of three different approaches leads to a good performance ADPLL controllable with fast lock-in algorithm Modified (smoothed) PID algorithm was introduced Future work: Further measurements 10th Sep

21 Thank you for your attention 10th Sep