RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
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1 RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London
2 RAPID PROTOTYPING OF DIGITAL SYSTEMS SECOND Table of Contents EDITION 1 Tutorial I: The 15 Minute Design 1.1 Design Entry using the Graphic Editor 1.2 Compiling the Design 1.3 Simulation of the Design 1.4 Downloading Your Design to the UP 1 or UP IX Board 1.5 The 10 Minute VHDL Entry Tutorial 1.6 Compiling the VHDL Design 1.7 The 10 Minute Verilog Entry Tutorial 1.8 Compiling the Verilog Design 1.9 Timing Analysis 1.10 The Floorplan Editor 1.11 Symbols and Hierarchy 1.12 Functional Simulation 1.13 For additional Information 1.14 Laboratory Exercises 2 The Altera UP 1 and UP IX CPLD Boards_ 2.1 Programming Jumpers 2.2 MAX 7000 Device and UP 1 I/O Features 2.3 MAX and FLEX Seven-segment LED Displays, 2.4 FLEX 10K Device and UP 1 I/O Features 2.5 Obtaining a UP 1 or UP IX Board and Power Supply 3 Programmahle Logic Technology 3.1 CPLDs and FPGAs 3.2 Altera MAX 7000S Architecture - A Product Term CPLD Device_ 3.3 Altera FLEX 10K Architecture - A Look-Up Table CPLD Device_ 3.4 Xilinx 4000 Architecture - A Look-Up Table FPGA Device
3 vi Rapid Prototyping of Digital Systems 3.5 Computer Aided Design Tools for Programmable Logic 3.6 Next Generation FPLD CAD tools 3.7 Applications offplds 3.8 Features of New Generation FPLDs 3.9 For additional information 3.10 Laboratory Exercises 4 Tutorial II: Sequential Design and Hierarchy_ 4.1 Install the Tutorial Files and UPlcore Library 4.2 Open the tutor2 Schematic 4.3 Browse the Hierarchy 4.4 Using Buses in a Schematic 4.5 Testing the Pushbutton Counter and Displays 4.6 Testing the Initial Design on the UP 1 Board._ 4.7 Fixing the Switch Contact Bounce Problem 4.8 Testing the Modified Design on the UP 1 Board. 4.9 Laboratory Exercises 5 UPlcore Library Functions 5.1 UPlcore DEC_7SEG: Hex to Seven-segment Decoder 5.2 UPlcore Debounce: Pushbutton Debounce 5.3 UPlcore OnePulse: Pushbutton Single Pulse_ 5.4 UPlcore Clk Div: Clock Divider 5.5 UPlcore VGASync: VGA Video Sync Generation, 5.6 UPlcore CHAR ROM: Character Generation ROM 5.7 UPlcore Keyboard: Read Keyboard Scan Code 5.8 UPlcore Mouse: Mouse Cursor 6 Using VHDL for Synthesis of Digital Hardware 6.1 VHDL Data Types 6.2 VHDL Operators 6.3 VHDL Based Synthesis of Digital Hardware 6.4 VHDL Synthesis Models of Gate Networks _ 6.5 VHDL Synthesis Model of a Seven-segment LED Decoder 6.6 VHDL Synthesis Model of a Multiplexer 6.7 VHDL Synthesis Model of Tri-State Output
4 vi Rapid Prototyping of Digital Systems 3.5 Computer Aided Design Tools for Programmable Logic Next Generation FPLD CAD tools Applications offplds Features of New Generation FPLDs For additional information Laboratory Exercises 52 4 Tutorial II: Sequential Design and Hierarchy Install the Tutorial Files and UPlcore Library Open the tutor2 Schematic Browse the Hierarchy Using Buses in a Schematic Testing the Pushbutton Counter and Displays Testing the Initial Design on the UP 1 Board Fixing the Switch Contact Bounce Problem Testing the Modified Design on the UP 1 Board Laboratory Exercises 61 5 UPlcore Library Functions UPlcore DEC_7SEG: Hex to Seven-segment Decoder UPlcore Debounce: Pushbutton Debounce UPlcore OnePulse: Pushbutton Single Pulse UPlcore Clk_Div: Clock Divider UPlcore VGASync: VGA Video Sync Generation UPlcore CHAR ROM: Character Generation ROM UPlcore Keyboard: Read Keyboard Scan Code UPlcore Mouse: Mouse Cursor 75 6 Using VHDL for Synthesis of Digital Hardware VHDL Data Types VHDL Operators VHDL Based Synthesis of Digital Hardware VHDL Synthesis Models of Gate Networks VHDL Synthesis Model of a Seven-segment LED Decoder VHDL Synthesis Model of a Multiplexer VHDL Synthesis Model of Tri-State Output 84
5 Table of Contents VII 6.8 VHDL Synthesis Models of Flip-flops and Registers Accidental Synthesis of Inferred Latches VHDL Synthesis Model of a Counter VHDL Synthesis Model of a State Machine VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter VHDL Synthesis of Multiply and Divide Hardware VHDL Synthesis Models for Memory Hierarchy in VHDL Synthesis Models Using a Testbench for Verification For additional information Laboratory Exercises 97 7 State Machine Design: The Electric Train Controller The Train Control Problem Track Power (Tl, T2, T3, and T4) Track Direction (DA1-DA0, and DB1-DB0) Switch Direction (SW1, SW2, and SW3) Train Sensor Input Signals (Sl, S2, S3, S4, and S5) An Example Controller Design VHDL Based Example Controller Design Simulation Vector file for State Machine Simulation Running the Train Control Simulation Running the Video Train System (After SuccessfuI Simulation) Laboratory Exercises A Simple Computer Design: The /JP Computer Programs and Instructions The Processor Fetch, Decode and Execute Cycle VHDL Model of the np Simulation of the npl Computer Laboratory Exercises VGA Video Display Generation Video Display Technology Video Refresh Using a CPLD for VGA Video Signal Generation 143
6 VIII Rapid Prototyping of Digital Systems 9.4 A VHDL Sync Generation Example: UPlcore VGA SYNC Final Output Register for Video Signals Required Pin Assignments for Video Output Video Examples A Character Based Video Design Character Selection and Fonts VHDL Character Display Design Examples A Graphics Memory Design Example Video Data Compression Video Color Mixing using Dithering VHDL Graphics Display Design Example Laboratory Exercises Communications: Interfacing to the PS/2 Keyboard PS/2 Port Connections Keyboard Scan Codes Make and Break Codes The PS/2 Serial Data Transmission Protocol Scan Code Set 2 for the PS/2 Keyboard The Keyboard UPlcore A Design Example Using the Keyboard UPlcore For Additional Information Laboratory Exercises Communications: Interfacing to the PS/2 Mouse The Mouse UPlcore Mouse Initialization Mouse Data Packet Processing An Example Design Using the Mouse UPlcore For Additional Information Laboratory Exercises Robotics: The UPI-bot The UPl-bot Design UPl-bot Servo Drive Motors Modifying the Servos to make Drive Motors 179
7 Table of Contents ix 12.4 VHDL Servo Driver Code for the UPl-bot 12.5 Sensors for the UPl-bot 12.6 Assembly of the UPl-bot Body 12.7 UPl-bot FLEX Expansion B Header Pins 12.8 An Alternative UP 1 Robot Pro.ject Based on an R/C Car 12.9 For Additional Information Laboratory Exercises 13 A RISC Design: Synthesis ofthe MIPS Processor Core 13.1 The MIPS Instruction Set and Processor 13.2 Using VHDL to Synthesize the MIPS Processor Core 13.3 The Top-Level Module 13.4 The Control Unit 13.5 The Instruction Fetch Stage 13.6 The Decode Stage 13.7 The Execute Stage 13.8 The Data Memory Stage 13.9 Simulation of the MIPS Design MIPS Hardware Implementation on the UP 1 or UP IX Board For Additional Information Laboratory Exercises Appendix A: Generation ofpseudo Random Binary Sequences Appendix B: MAX+PLUS II Design and Data File Extensions Appendix C: UP 1 and UP IX Pin Assignments Appendix D: The Wintim Meta Assembler Appendix E: An Introduction to Verilog for VHDL users Glossarv Index About the Accompanying CD-ROM
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