IEE5008 Autumn 2012 Memory Systems 3D Nand Flash Memory

Transcription

1 IEE5008 Autumn 2012 Memory Systems 3D Nand Flash Memory Department of Electronics Engineering National Chiao Tung University 2012

2 Outline Introduction Planar Nand Flash Technology Limitations in 2D Nand 3D Integration Vertical Channel 3D Nand Memory Vertical Gate 3D Nand Memory Effects of Noise Conclusion Reference 2

3 Introduction Memory Technology Figure 1. Memory technology taxonomy [13] Source: M. Wang, Technology trends on 3D-Nand flash memory, Impact Taipei,

4 Nand Memory Scaling Sub 20nm possible. Sub 10nm? Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Figure 2. Nand memory scaling trend [13] 4

5 Nand Flash Scaling Issues How much can we scale down the cell? Dielectric thickness current leak, breakdown Data retention, endurance How many electrons in cell? Restricted MLC operation Few electrons below 10nm Cell operation Operating voltages Noise performance cross talk 5

6 Number of Eleectrons Figure 3. Number of electrons per logic level [13] 6

7 3D INTEGRATION TECHNOLOGY Lateral scaling limited Scaling in vertical direction Ground Car Parking Lot Multi level Car Parking Lot 7

8 3D Integration Options 3D stacking performance Cost effective? TSV technology Still expensive Nand flash memory specific technology 8

9 3D Nand Flash Technology Vertical Channel Nand Flash Memory Bit Cost Scalable (BiCS) Nand Pipe-shaped Bit Cost Scalable (P-BiCS) Nand Vertical Stack Array Transistor (VSAT) Nand Terabit Cell Array Transistor (TCAT) Nand Vertical Gate Nand Flash Memory Vertical Gate Nand PN diode decoding Independent Double Gate Single Crystalline Stacked Array (STAR) Nand 9

10 Bit Cost Scalable (BiCS) Nand Few constant number of critical lithography process steps Punch and Plug process Figure 5. (a)bird eye view of BiCS Nand, (b) top down view [1]. 10

11 Fabrication Process Lower select gate transistor, memory string and upper select gate transistor are fabricated individually. Gate material is P+ poly-si. Holes for transistor channel or memory plug are punched through and LPCVD TEOS film or ONO films are deposited. The bottom of dielectric films are removed by RIE and plugged by amorphous Si. Arsenic is implanted and activated for drain and source of upper device. Edges of control gate are processed into stair-like structure by repeating of RIE and resist sliming. For minimizing disturb, whole stack of control gate and lower select line are etched to have a slit. Upper select gate is cut into line pattern to work as row address selector. Via hole and BL are processed on the array and peripheral circuit simultaneously. Figure 6. Fabrication steps [1] 11

12 Pipe-shaped BiCS Nand BiCS limitations Small P/E window, read disturb and low data retention Doubtful for MLC operation Variation in voltage due to numerous cells on the same string cause LSG in heavily doped source makes diffusion profile difficult to control P-BiCS pipe-like Nand string structure One terminal connected to BL and the other to SL 12

13 Fabrication The first step is the PC formation. The next step is the deposition of the sacrificial films followed by memoryhole formation. For multiple layers multiple layers of memory films should be deposited. The SG transistors are formed after the fabrication of the Nand strings. After SG-hole formation the sacrificial films are removed. The removal of the sacrificial film leaves a U-pipe that connects two vertical Nand cells strings. Next the memory films are deposited and silicon deposition is done last Figure 7. Fabrication steps [2] 13

14 Advantages over BiCS larger P/E window higher operating speed higher data retention of with no degradation after 10 years V th shift of less than 0.3 V after 100k cycles of read operation at 7.5 V Figure 8. P-BICS architecture [2] data retention and the immunity to read disturb are sufficient for MLC operation 14

15 Vertical-Stacked Array Transistor (VSAT) BiCS and P-BiCS have stair like structure for peripherals Takes larger area VSAT removes the stair structure Figure 9. VSAT architecture, improvised base interconnect and staircase base [3] 15

16 Fabrication A Si mesa is prepared by dry etching. Over this Si mesa multiple layers of gate electrodes and isolating films of poly-doped-silicon and nitride are deposited. The active regions are created through lithography followed by dry etching. Multiple WLs are patterned using KrF lithography followed by dry etching. All the gate electrodes are exposed on the same plane after a CMP process. The tunneling-oxide, charge-trapping-nitride, and control oxide films are deposited in turn on the active region, followed by a poly-silicon deposition process of the channel material. Finally, to isolate vertical strings, an etching process is carried out. Figure 10. Fabrication steps [3] 16

17 Terabit Cell Array Transistor (TCAT) Metal gate structure Difficult etching metal/oxide multilayer simultaneously good erase speed, wider V th margin, and better retention GIDL erase of BiCS flash area overhead limited erase voltage Figure 11. TCAT architecture [4] 17

18 Structural Changes Oxide/nitride multilayer stack sacrificial nitride layer is removed by wet removal process Line-type W/L cut dry etched through the whole stack between the each row array of channel poly plug Line-type CSL formed by an implant through the W/L cut W/L cut has no additional area penalty Metal gate lines for each row of poly plug. Gate replacement process implemented to achieve the metal gate SONOS structure 18

19 Advantages over BiCS The channel poly plug connected to Si substrate Implementation of bulk erase operation without any major peripheral circuit changes. Smaller area overhead than BiCS flash 19

20 Vertical Gate Nand Flash Memory Limitations of Vertical Channel Nand BiCS Nand flash has difficulty with WL interconnect, program disturbance, and channel resistance and they get worse as the number of WL between top BL and bottom CSL increases P-BiCS and TCAT have structures such that the channel current is conducted through a hole drilled through the layers in the vertical direction, and an additional WL-cut process must be applied to isolate the WL s in the X direction. They have limited X pitch scalability due to the corresponding lithography overlay issue involved. The cell size of all vertical channel architectures is 6F 2 which is relatively large and does not correspond to the traditional planar Nand cell size As the number of layers increases, the read current inevitably degrades due to the increase in the length of the NAND string 20

21 Vertical Gate Nand Architecture WL and BL are formed at the beginning of fabrication before cell array making interconnect between WL, BL and decoder easier Source and active body (V bb ) are electrically connected to CSL Enable body erase operation To perform erase operation a positive bias is applied to CSL Array schematic is similar to that of a planar Nand except SSL Common BL and common WL between multi-active layers to select data from a chosen layer out of multi-layers 21

22 VG Nand Architecture Figure 12. Vertical gate Nand flash structure [5] 22

23 Fabrication Integration scheme is based on simple patterning and plugging. BL with n+ poly-si is fabricated first and then n+ poly-si WL is formed on top of it. Multi-active layers with p-type poly-si are formed with n-type ion implants for SSL layer selection Alternated inter-layer dielectrics are inserted between actives. Patterning is done on the multi-active layers and charge trap layers (ONO) are deposited over the patterned actives. Consecutively VG is formed and connected to WL. In the final step, vertical plugs of DC and Source-V bb are connected to BL and CSL after contact ion implants. N+ doped source and p-type active are electrically tied to CSL. Figure 13. Fabrication steps [5] 23

24 VG Nand Features Each device double-gate TFT BE-SONOS The channels are all n-type doped poly (buried-channel) improves read current allows implementation of the junction-free structure required for 3D stackable devices The conventional WL s and BL s are grouped into planes. The conventional BL contact is replaced by the SSL. The intercept of the three selected planes (WL, SSL, and BL) defines the selected memory cell Difficult to isolate SSL gate in the X-direction and can limit the pitch scalability of the cell plural SSL fabrication limits scalability Need simple and highly scalable decoding circuit and array 24

25 Improved Architecture PN diode decoding Self-aligned independent double-gate (IDG) (a) (b) Figure 14. (a) PN diode VG Nand [7], (b) self aligned independent double gate [8] 25

26 VG PN Diode Architecture Fabricated as self-aligned at the source side of the vertical gate P+ ion implantation or P+ poly plug process Plural string select (SSL) transistors inside the array completely eliminated. array structure is now simpler highly scalable 1/2-pitch scalability to 2Xnm node or below layout is similar to that of the conventional 2D Nand Symmetrical and scalable cell structure Prevents leakage of self-boosted channel potential. channel is fabricated lightly-doped n-type (buried-channel) higher the read currents 26

27 VG IDG Architecture Independently controlled double gate (IDG) TFT BE-SONOS string select transistor (SSL) improved decoding Implemented by stripping the top portion of SSL poly gate after WL patterning Every SSL is independently connected through the interconnection of CONT, ML1, VIA1, and ML2 toward the SSL decoder Each unit has 2N ploy-channel BLs; N is stacked memory layers BLs are controlled by the corresponding 2N SSLs fabricated on N staircase BL contacts are fabricated. Each BL corresponds to one memory layer. Stacked VIA/CONT connect the staircase BL contacts to ML3 BL s and the page buffer for sensing. Common source line (CSL) fabricated; connects all sources lines of every memory layers. 27

28 VG IDG Decoding Circuitry Cell select by intercept of WL, ML3 BL and page. unselected adjacent pages are inhibited inhibit bias (V inhibit ) at the other SSL gate Assuming memory chip with M (such as 16Kb) channel BL s, and N (such as 8) memory layers. Since the ML3 BL has double X pitch, the total number of ML3 BL number is M/2 (8Kb), while the total unit number is M/16 (1Kb). Every unit has 2N (16) pages, defined by the sandwich of two adjacent SSL s. To select one page (such as SSL0/1) for each WL (such as WL30), it selects M/16 (1Kb) SSL devices in parallel units. By allowing all-bitline (ABL) sensing for the 8- layers together, the total selected devices are 1Kb*8=8Kb (M/2), which is the page size. Increasing memory stacks doesn t decrease the array layout efficiency but change the BL pad layout and the associated page number. Figure 15. VG Nand decoder circuit [11] 28

29 Single Crystalline Stacked Array (STAR) VG Nand has issues area overhead due to SSL transistors Additional photolithography and ion-implantation steps at each stacked layer to make the SSLs Design goals: good compatibility with peripheral memory functional blocks operation methods similar to the 2D Nand Flash lesser throughput penalty related with page program, block-erase, and page read New unit of 3-D structure, i.e., building Figure 16. Building model [9] 29

30 STAR Architecture BLs are formed on the top floor of a building perpendicular to lines WLs and SSLs which are parallel with different levels. Longer gate length of the SSL transistor reduces leakage current Now area penalty Gate-all-around (GAA) structure of SSL maintains excellent current drivability N+ doped CSL and p-type body are electrically tied The channel connected to a p-type body bulk erase operation Figure 17. STAR architecture [9] 30

31 Fabrication Steps SiGe/Si layers formed sequentially and epitaxially grown on the Si substrate Active channel formed and n- and p-type ion implantations made for the BL region and body, respectively High dose n-type ion implantation performed to make the N+ CSL region. Oxide deposition is followed by patterning the oxide buttress, selective SiGe etching process carried out. Oxide re-deposition to fill the gap between Si channels Oxide patterning carried out for making WLs Cell silicon channel is exposed by isotropic oxide etch Growth of ONO dielectrics is followed by tungsten deposition and planarization for the gate of WL, SSL, and GSL. Damascene gate process ensures all gates of cell, SSL, and GSL transistors are self-aligned. SSL transistors are made by lithography [(h) and (i)]. BL region is made by carrying out trench etch. SiGe selective etch is performed for perfect isolation between the BLs [(j) and (k)]. Finally, the stair-like BL structure is created. 31

32 Fabrication Steps Figure 18. Fabrication steps [10] 32

33 Advantages Better scalability Less sensitive to 3-D interference Stable virtual source/drain characteristics Better extendibility over other stacked structures. No grain boundaries Better cell performance GAA structure large BL read current small sub-threshold swing Figure 19. I d V g characteristics [9] 33

34 Advantages Stable virtual source/drain (S/D) characteristic Small intra-layer interference Immunity to interlayer interference Small channel channel (Ch Ch) coupling The unit cell size of STAR is larger than that of VG NAND because O/N/O gate dielectric layers are formed along oxide buttress during damascene gate process. Figure 20. Ch Ch coupling phenomenon between stacked channels [9] 34

35 Noise Effects Analysis To be discussed and explored in the future impact on the performance and scalability Most vertical channel Nand technology uses on poly-silicon as a channel material Random Trap Fluctuation (RTF) Random Telegraph Noise (RTN) Modeling RTF and RTN important to predict V T distribution for 3D Nand devices that implement MLC operation. 35

36 Random Trap Fluctuation (RTF) Due to fluctuations of the traps location inside Poly- Si channel Traps follow a Poisson statistics traps density a reliable metric for evaluating the electrical performance of Poly-Si channel 36

37 Random Telegraph Noise (RTN) Induced as a result of RTF in poly-si follow an exponential distribution RTN energy distribution shows most of RTN traps are present at Fermi level induced during program operation by the cycling of the cell. 37

38 Simulations and Measurements Figure 21. Noise analysis of 3D Nand flash [10] 38

39 Conclusion Planar Nand will be completely replaced by 3D Nand 3D Nand promises to satisfy the growing need of Nand memory Table 1. Comparison of 3D Nand flash memory architectures Comparison of 3D Nand flash memory architectures Vertical Channel Vertical Gate P-BiCS [1] VSAT [2] TCAT [3] Vertical Gate [6] STAR [9] Cell Size 6F 2 6F 2 6F 2 4F 2 6F 2 Current Flow Direction U-turn Vertical Vertical Horizontal Horizontal Device Structure GAA Planar GAA Double Gate GAA Possible Minimum F ~50nm ~50nm ~50nm 2xnm ~30nm Impact of number of layers of memory Low read current Low read current Low read current No impact No impact 39

40 Conclusion Figure 22. Transition from 2D to 3D Nand memory [12] 40

41 Reference 1. Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory H.Tanaka, M.Kido, K.Yahashi, M.Oomura, R.Katsumata, M.Kito, Y.Fukuzumi, M.Sato, Y.Nagata, Y.Matsuoka, Y.Iwata, H.Aochi and A.Nitayama, IEEE Symposium on VLSI Technology, pp , Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Yuzo Nagata, Li Zhang, Yoshihisa Iwata, Ryouhei Kirisawa*, Hideaki Aochi and Akihiro Nitayama, Symposium on VLSI Technology, pp , Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive) by Jiyoung Kim, Augustin J. Hong, Sung Min Kim, Emil B. Song, Jeung Hun Park, Jeonghee Han, Siyoung Choi, Deahyun Jang, Joo -Tae Moon, and Kang L.Wang, Symposium on VLSI Technology, pp , Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory by Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Younggoan Jang, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim, Kihyun Kim, Jae-Joo Shim, Jin Soo Lim, Kyoung-Hoon Kim, Su Youn Yi, Ju-Young Lim, Dewill Chung, Hui-Chang Moon, Sungmin Hwang, Jong- Wook Lee, Yong-Hoon Son, U-In Chung and Won-Seong Lee, Symposium on VLSI Technology, pp , Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage Wonjoo Kim, Sangmoo Choi, Junghun Sung, Taehee Lee, Chulmin Park, Hyoungsoo Ko, Juhwan Jung, Inkyong Yoo, and Yoondong Park, Symposium on VLSI Technology, A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device by Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, and Chih-Yuan Lu, Symposium on VLSI Technology,

42 Reference 7. A Highly Scalable Vertical Gate (VG) 3D NAND Flash with Robust Program Disturb Immunity Using a Novel PN Diode Decoding Structure Chun-Hsiung Hung+, Hang-Ting Lue, Kuo-Pin Chang, Chih-Ping Chen, Yi-Hsuan Hsiao, Shih-Hung Chen, Yen-Hao Shih, Kuang-Yeu Hsieh, Mars Yang, James Lee, Szu-Yu Wang, Tahone Yang, Kuang-Chao Chen, and Chih-Yuan Lu, Symposium on VLSI Technology, A Highly Pitch Scalable 3D Vertical Gate (VG) NAND Flash Decoded by a Novel Self-Aligned Independently Controlled Double Gate (IDG) String Select Transistor (SSL) by Chih-Ping Chen, Hang-Ting Lue, Kuo-Pin Chang, Yi-Hsuan Hsiao, Chih-Chang Hsieh, Shih-Hung Chen, Yen-Hao Shih, Kuang-Yeu Hsieh, Tahone Yang, Kuang-Chao Chen, and Chih- Yuan Lu, Symposium on VLSI Technology, Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline STacked Array by Yoon Kim, Jang-Gn Yun, Se Hwan Park, Wandong Kim, Joo Yun Seo, Myounggon Kang, Kyung-Chang Ryoo, Jeong-Hoon Oh, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, IEEE Transactions on electron devices, vol. 59, no. 1, January Intrinsic Fluctuations in Vertical NAND Flash Memories by Etienne Nowak, Jae-Ho Kim, HyeYoung Kwon, Young-Gu Kim, Jae Sung Sim, Seung-Hyun Lim, Dae Sin Kim, Keun-Ho Lee, Young-Kwan Park, Jeong-Hyuk Choi, Chilhee Chung, Symposium on VLSI Technology, Integrated circuit self-aligned 3D memory array and manufacturing method, US Patent - US A1, D Approaches for Non-volatile Memory by Jungdal Choi, Kwang Soo Seol, IEEE Symposium on VLSI Technology, pp , Technology Trends On 3D-NAND Flash Storage, Michael Wang, Impact Taipei, 2011, 42

43 43