Flash Memories. João Pela (52270), João Santos (55295) December 22, 2008 IST

Transcription

1 Flash Memories João Pela (52270), João Santos (55295) IST December 22, 2008 João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

2 Layout 1 Introduction 2 How they work 3 The Floating Gate Device 4 NOR vs NAND 5 Flash memory as a replacement for hard drives 6 Developments in Flash Memories João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

3 Introduction João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

4 Introduction - Memory types Volatile (temporary storage RAM DRAM SDRAM... Non Volatile (permanent storage) Tape (Magnetic Storage) Hard Disks (Magnetic Storage) ROM - Not programable PROM - Programable once EPROM - High density, long erase time that needs UV light EEPROM - Lower density, electrically erasable FLASH - High density, electrically erasable... João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

5 Introduction - Motivation for FLASH I System Designers have long dream of a non volatile memory which could be electrically erased and programmed in-system. offering at same time very high-density and low cost-per-random access, bit alterability, short read/write times and cycle, excellent reliability. In most of the current systm applications, these features should be also combined with low power consumption and single, low-voltage, power supply operation. The FLASH memory technology has many of the characteristics of the ideal memory concept João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

6 Introduction - Motivation for FLASH II FLASH Memories are: Non-Voltatile single cell can be electrically programmed a block (large number of cells) are electrically erasable at the same time the whole memory can be erase at once high density (like EPROMs) electrically in-system erasability (like EEPROM) João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

7 Introduction - FLASH Applications Integration in Logic Systems Microprocessors - to allow software updates, store identification codes,... Cache in Hard Disks - Has a temporary storage space for data block that are read (or frequently read) from disk, in order to minimize the access time Cache in Main Boards - Has a temporary storage space for frequently executed binaries blokes in order to reduce need to access secondary storage devices (that are slower)... Storage Elements Flash Solid State Disks - Compact and Robust, storage elements composed of FLASH memory arrays Flash USB Drives, Memory Cards,... - Portable memory elements that can have considerable space... João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

8 How they work João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

9 Flash Memories - How they are built Built with cells, each one is like a standard MOSFET only with two gates instead of one; Like in MOS transistors the control gate (CG) is on top, but there is a floating gate (FG) insulated all around by an oxide layer; The FG is placed between the CG and the channel from the MOSFET, as the FG is electrically isolated the electrons are trapped there (with normal conditions it will not discharge for years). João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

10 Flash Memories - How they work When the FG is charged, it partially cancels the electric field from the CG, thus modifying the threshold voltage of the cell; During the reading procedure, a voltage is applied to the CG resulting in the MOSFET channel becoming conducting ou remaining insulated, depending on the cell s threshold voltage (which is controlled by the charge in the FG); The stored data is reproduced in the form of a binary code, which is the result of the current passing in the MOSFET channel during the read procedure; In the case of a multi-level cell device, that stores more than one bit per cell, it s the amount of current instead the its presence or absence that determines more precisely the level of charge on the FG; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

11 Flash Memories - Programming A single-level flash cell in the default state is equivalent to a binary 1 value, because current will flow through the channel under application of an appropriate voltage to the control gate; The cells can be programmed, set to binary 0, with the following procedure: an elevated on-voltage, typically larger that 5V, is applied in the CG; this turns the channel on, allowing electrons to flow from the source to the drain; this current is sufficiently high to cause some high energy electrons to cross the insulating layer onto the FG, via a process called hot-electron injection. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

12 Flash Memories - Erasing For erasing a flash cell, resetting to binary 1, a large voltage of the opposite polarity is applied between the CG and the source, this pulls the electrons of the FG through quantum tunneling. Modern flash memory chips are divided into erase sectors, and the erasing operation is performed by sectors (all the cells in a sector are erased together). The programming of cells can generally be performed one byte or word at a time. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

13 The Floating Gate Device João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

14 The Floating Gate Device I Consider the schematic on the figure. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

15 The Floating Gate Device II We can use this simple electrical model. C C, C S, C D and C B are the capacitance between floating gate (FG) and control gate, source, drain and bulk regions, respectively. V C, V S, V D and V B are the control gate, drain, source and bulk pontentials, respectively. Q is the Charge within the FG. C T = C C + C S + C D + C B is the total capacitance The FG potencial V F is: V F = C C C T V C + C S C T V S + C D C T V D + C B C T V B + Q C T (1) João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

16 The Floating Gate Device III If source and bulk are both grounded and all potencials are referred to the source, we get: V FS = C C C T V CS + C D C T V DS + Q C T (2) We can define α C = C C C T as the coupling factor and f = C D C C, so we get: V FS = α C (V CS + fv DS + Q C C ) (3) The characterstics of a FG device depend on the threshold voltage, that is the potencial V TFS that must be applied to the FG (with V DS = 0) to reach inversion of the surface population. Since the floating gate cannot be accessed, V TFS is applied to the floating gate when a suitable voltage V TCS, to be derived from last equation, is applied to the control gate: V TCS = 1 α C V TFS Q C C (4) João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

17 The Floating Gate Device IV We get the following graphics for I DS in terms of V CS. We can graphical see what should be tension applied to the control gate so we can be sensitive (in a logical way) to the charge in the floating gate João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

18 The Floating Gate Device V We can now define the voltage thresholds for a functional Flash Memory cell. Where a erased state has Q = 0, and a programmed with a charge Q Q << 0 on the FG: V TCS = 1 α C V TFS = V TE (5) V TCS = 1 α C V TFS Q C C = V TP (6) João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

19 NOR vs NAND João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

20 Flash Memories - NOR vs NAND NOR and NAND flash differ in two important ways: the connections of individual memory cells are different the interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only page access) These differences are due to the design choices made in the development of NAND flash; The goal of the NAND flash development was to reduce the chip area required to implement a given capacity, thus reducing the cost-per-bit and increasing maximum chip capacity, allowing flash memory to compete with magnetic storage devices; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

21 Flash Memories - NOR I NOR and NAND flash memories get their name due to the structure of the interconnections between memory cells: The NOR flash cells are connected in parallel to the bitlines, this allow cells to be programmed and read individually; This parallel connection of cells resembles the parallel connection of transistors in a NOR gate. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

22 Flash Memories - NOR II The NOR flash was created to be a more economical and conveniently rewritable ROM than the existent EPROM and EEPROM memories; This considered a random-access reading circuitry was necessary; As it was expected that NOR flash memory would be read more often than written, the write circuitry included was slow and could only erase in block (random-access write circuitry would add to the complexity and cost unnecessarily); João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

23 Flash Memories - NOR III NOR: Internally in a NOR flash, the individual memory cells are connected in parallel this enables random access to the memory; This internal configuration enables short reading times required for random access of microprocessor instructions; This type of flash is ideal for lower-density, high-speed read applications, which are mostly read only (referred as code-storage applications); João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

24 Flash Memories - NAND I In the case of NAND flash memory, the cells are connected in series, like a NAND gate; This prevents the cells from being read and programmed individually, the cells must be read in series; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

25 Flash Memories - NAND II The series connection and removal of wordline contacts in NAND flash allow the grid of memory cells to occupy only 60% of the area of equivalent NOR cells; The area and cost of a NAND chip was further reduced by the removal of the external address and data bus circuitry; This way external devices could communicate with the NAND flash via sequential-accessed command anda data register, which would internally retrieves and output the necessary data. However, this design choice made random-access of NAND flash memory impossible; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

26 Flash Memories - NAND III NAND: The NAND flash was created as an alternative which is optimized for high-density data storage, achieving a smaller cell size on the lost of the random access capability; These smaller cells result in smaller chip size and lower cost-per-bit; This was obtained by creating an array of eight memory transistors connected in series; This architecture of high storage density and smaller cell size, enables faster write and erase by programming blocks of data; NAND flash is ideal for low-cost, high-density, high speed program/erase applications (referred as data-storage applications); João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

27 Flash Memories - NOR vs NAND PARAMETER NOR NAND Capacity 1 to 16 Mbytes 8 to 128 Mbytes XIP (code execution) Yes No Erase Very Slow (5 s) Fast (3 ms) Write Slow Fast Read Fast Fast Strengths Addressable to every byte More than 10% higher life expectancy Interface 10,000 to 100, ,000 to 1,000,000 Erase cycle range SRAM-like, memory mapped Accessed in bursts of 512 bytes; I/O mapped Access method Random Sequential Price High Very low Data from 2002 João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

28 Flash memory as a replacement for hard drives João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

29 Types of flash Memories - Flash memory as a replacement for hard drives An extension of flash memory is the replacement of hard drives; The advantages of flash memory compared to hard disk drives are higher speed and reliability and lower noise and power consumption; The disadvantages are that the cost per gigabyte of the flash memory are higher than the nowadays hard drives, though the ratio is decreasing rapidly for flash memory; There is also concern that the finite number of erase/write cycles of flash memory would render flash memory unable to support an operating system; Some companies are already releasing flash memory based PC s and hard drives; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

30 Developments in Flash Memories João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

31 Flash memory scaling - Developments in Flash Memories The scale of flash memory is in sub-100-nm lithography regime; Due to this scaling is becoming a greater challenge due to the high electric fields required for it to function; These requirements are imposing fundamental scaling limitations on the cell operating voltages and on the physical thickness of the tunnelling dielectric; In order to overcome these limitations it will be required innovations in cell structure and device materials; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

32 Flash memory scaling - Scalling challenges and alternatives Since the development of flash memory, the size of the cells has been reduced through a combination of lithography and self-alignment techniques; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

33 Flash memory scaling - Scaling challenges and alternatives I Nowadays, is common for many of the cell components to be fully of partially sellalligned; This eliminates the need for lithography registration between the layers; The picture illustrates various self-alignment techniques; When the cell becomes completely self-aligned, further scaling is determined by the electrical limiters of the cell; This means that scaling the cell requires scaling the capacitive network and basic transistor features. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

34 Flash memory scaling - Scaling challenges and alternatives II Self-alignment techniques. Use of a self-aligned source (SAS), self-aligned poly (SAP) floating gate, and unlanded contact (ULC) eliminates most lithography registration components of the flash cell area.the dotted box represents one unit memory cell within an array.lambda is the minimum lithography feature size; ILD = interlayer dielectric; STI = shallow trench isolation. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

35 Flash memory scaling - Channel-Length Scaling I In order to achieve hot carrier programming, a voltage of about 4 V is required from the drain to the source to produce electrons to overcome the 3.2 ev Si-Sio2 barrier height; The historical scaling trend for channel length can be extrapolated for potential limits, which are based on the fact that scaling is achieved by reducing specific cell dimensions; The convergence point represents a projection of a scaling rate limiter of the current planar cell structure, scaling the gate length will be limited below the 70 nm lithography node due to the inability of the shorter channel length to withstand the required programming voltage; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

36 Flash memory scaling - Channel-Length Scaling II Alternatively the channel length scaling could be achieved through the engineering of the Si-SiO2 barrier; If a different dielectric is choose the barrier could be tailored to allow the hot carrier injection to occur at lower voltages; Other alternatives to address the gate-length scaling constraint are three-dimensional structures in the transistors; Two types of this structure are fin and U, which allow further scaling while maintaining the channel length required for programming; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

37 Flash memory scaling - Channel-Length Scaling III Example of finfet type of flash cell with vertical storage gate. This structure moves the channel-length constraint into the vertical direction, allowing further x y scaling to occur. João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

38 Flash memory scaling - Tunnel Oxide Scaling Challenges and Alternatives I The scaling of the tunnelling oxide is a primary limitation to the cell scaling; The tunnel oxide needs to scale to enable channel length scaling, but this is not possible, due to data retention requirements; The requirements of charge retention set a lower limit for the tunnel oxide thickness of about 80 Å, due to stress-induced low-field tunnelling; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

39 Flash memory scaling - Tunnel Oxide Scaling Challenges and Alternatives II The International Technology Roadmap for Semiconductors (ITRS) revealed a tunnel oxide scaling roadmap that was made more conservative in the 2001, due to the difficulties of going below 80 Å. Considering this, it is clear that to enable a significant reduction below 80 Å, a change in the SiO2 dielectric is required; Already alternative materials are being explored for this, in particular, crested barrier composite films are considered promising to enable the design of a more optimal barrier structure; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

40 Flash memory scaling The flash memory devices are pushing into the sub-100-nm lithography regime; Device scaling is becoming more challenging due to the high electric fields required for the programming and erase operations and the stringent leakage requirements for long term charge storage; Overcoming these limitations will require innovations in cell structure and device materials; Three dimensional structures and self-alignment techniques can address the physical scaling issues; High-dielectric-constant and crested barrier (or barrier-engineered) materials can address the dielectric scaling issues; It is projected that flash scaling can progress at the current rate through at least the end of the decade using techniques that are available today; João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41

41 Bibliography Flash Memories, Paulo Cappelletti, Carla Golla, Piero Olivo and Enrico Zanoni; Flash Memory Scaling, Al Fazio High-Performance Emerging Solid-State Memory Technologies, Herb Goronkin and Yang Yang João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, / 41