Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors

Transcription

1 Fabrication and Characterization of N- and P-Type a-si:h Thin Film Transistors Engineering Practical Jeffrey Frederick Gold Fitzwilliam College University of Cambridge Lent 1997

2 FABRCATON AND CHARACTERZATON OF n- AND p-type a-si:h THN FLM TRANSSTORS Jeffrey Frederick Gold ntroduction UNVERSTY OF CAMBRDGE CAVENDSH LABORATORY CAMBRDGE CB3 OHE Herein we describe the fabrication and characterization of n- and p-type amorphous silicon thin film transistors (TFTs). The planar, inverted-staggered, type A ( unpassivated) TFTs described were fabricated as part of the laboratory practicals of the 1996 MPhil program in Microelectronic Engineering and Semiconductor Physics. Fabrication The fabrication procedures consisted of the following: 1. Substrate preparation in clean-room conditions. 2. Deposition of silicon dioxide (Si0 2 passivation layer in PECVD system. 3. Annealing step was not performed (and ultimately affected device quality). 4. Deposition of a-si: H layer. Figure 1: Geometry and composition of n channel "keyhole" a-si:h TFT. illustration adapted from [3]. 5. Deposition of doped (n+ ) a-si:h layer. 6. Deposition of chromium and aluminum (only aluminum in the case of p-type TFT). 7. Photolithography of a-si:h TFT channel region. 8. P hotolit hography of a-si:h island region (see Figure 3). 9. Devices were never annealed because fabrication processes failed (bonding of photo-resist to exposed surfaces) near end of fabrication procedure. All devices described henceforth are from previous years. Cross-sectional view of TFTs is shown in Table 1 below. The final geometrical configuration and stratigraphy is given in Figures 1 and 2. 1

3 Characterization 1m Glass Substrate 0 a-si:h ~ Gate nsulator Electrodes n-type a-si:h Figure 2: Stratigraphy of inverted-staggered n channel type-a (unpassivated) TFT. illustration adapted from [3]. The bias stressing of the transistors consisted of the following procedures: 1. Measurement of TFT "as is" Volt bias anneal. 3. Measurement of annealed TFT. 4. stress TFT at +20 Volts at 75 C for 1000 sec. 5. Measurement of stressed TFT Volt bias anneal. 7. Measurement of annealed TFT. 8. stress TFT at -20 Volts at 75 C for 1000 sec. 9. Measurement of stressed TFT Volt bias anneal. 11. Measurement of annealed TFT. Figure 3: Talystep (SLOAN DECTAC ) measurement showing lengthwise cross-section of n-type keyhole structure. Layer Thickness Aluminum 1000 A Chromium 1000 A n-type Si 500 A a-si:h 3000 A Si A c-si ~ 0.5 mm Table 1: Cross-sectional view of TFTs. n the p-channel TFT, the chromium layer is missing. Here, the bottom layer is the substrate. Discussion P-channel devices were created by allowing aluminum to diffuse into the amorphous silicon. n n-channel devices, a chromium barrier layer was deposited before the deposition of aluminum. The physics of MOS (metal-oxide-silicon) devices is relevant to our discussion of the electrical characteristics of these devices [1][4]. nterface traps and oxide charges affected the device performances, although for hydrogenated amorphous silicon, the defect density is greatly reduced. These defects tend to control many of the electrical characteristics of the material and are responsible for the characteristic metastability. 2

4 Stressing of TFTs n the bias stressing test, in which weak Si-Si bonds were broken with resulting defect formation by the injection of charge carriers at the a-si:h/insulator interface, we found that device characteristics, such as electron J?Obilities, threshold voltages, and pre-threshold slopes (PTS), for example, were altered. The physics behind these device characteristics proposes that the defect state density moves upward past the Fermi level for the negative bias stress and moves down for the positive bias stress, according to the defect model [2]. Even though the devices were bias annealed, there was evidence of migration of device characteristics, especially in the case of p-channel TFTs. That is to say, the formation and destruction of defect states was not as reversible in p-channel devices as in the case of n-channel devices. n the case of the positive bias stress test for the p-channel devices, the drain current increased after the test, indicating a higher threshold voltage at the gate. We extracted the following TFT parameters: PTS State Mobility Vt 0 V Anneal v V Anneal v V Anneal Table 2: The effects of annealing and bias stressing on n-channel device mobility, threshold voltage (Vt), and pre-threshold slope (PTS). The sub-threshold voltage is of interest because it gives an indication of the density of states in the bandgap. As the voltage increases, the density of states move higher into the bandgap region toward the conduction band, first through a linear region, and then State Mobility Vt PTS 0 V Anneal v V Anneal v V Anneal Table 3: The effects of annealing and bias stressing on p-channel device mobility, threshold voltage (Vt), and pre-threshold slope (PTS). later, as the voltage increases, into a saturation region. Amorphous silicon ( a-si) is slightly n type by its very nature because of the higher number of defects and higher dangling bond density [2]. Threshold Voltages and Pre- Threshold Slopes Both n- and p-type devices, when subjected to the +20 V and -20 V bias tests, demonstrated that the threshold voltages increased (see Tables 2 and 3). This means that higher voltages are required to activate the device, a facet also realized from the rather "shallow" prethreshold slopes. The plots for pre-threshold slopes are given in Figures 4 and 5. C-V Characteristics We observed the shifting of the C-V characteristic curves as a result of the resident oxide charge. The p-channel devices displayed more hysteresis than n-channel devices. Electron Mobility Note that p-channel device mobility is off by a factor of 3 from n-channel device mobility. This is in keeping with the retarded mobilities of holes with respect to electrons. However, 3

5 .26 r-.--r r... ~r--r-.--, :~~ ~ -r--, t-+, t-+--i til ~ :~: " _.-... =r=r= -v z 1 ~ - ;N~!tan el PH t--+--t----'1--t--+--t.06 L '---'---'----L----<'--...., Figure 4: N -channel Pre-Threshold Slope (PTS) vs ;0~.12 ~.1 1l ~ z.04 v JP' --'-"" &N- har ne M bil ty.02 Figure 6: N-channel Mobility vs.. Here the 0 Volt data imply annealing was carried out with no bias prior to measurement, as in Table til ~ 1l =....c: -.5 u ~ /. v : ;;?" ),--' / v r----- ~ -- ~ / P-c "an rtel TS Figure 5: P-channel Pre-Threshold Slope (PTS) vs.. P-channel devices displayed more meta-stability than n-channel devices, that is to say, device characteristic values in p channel devices did not readily return to initial values after 0 V bias annealing as did n-channel devices after stress testing. the mobilities exhibited in our n-channel devices were approximately one order of magnitude less than expected values. The mobilities for the bias stressing tests are plotted in Figures 6 and 7. Conclusion Device and fabrication failure made it difficult to extract any meaningful data for analysis; however, we characterized the devices and extracted such information as electron mobilities, threshold voltages, and pre-threshold slopes from the data obtained. Acknowledgements would like to thank our lab assistants for their lively discussions and enthusiasm throughout the practicals. would also like to express my gratitude to my teammates, Jason Lin Tan (Downing) and Steven Keller (Churchill). 4

6 -.042 ~~~~f---':ll'<:,"\ ,e ~ t--A/)"<:'\"'.:l\.-t ::s w-+-~~~ g t--+-+-t.~+--1-~-t ~ -.05 ~~---41ff -+-+-l--+-~~-+--l ] A '. ; "~ -. ~ V 1-ch nnel ~ ob lil] L..-.L...L J...-..J J L...-J Figure 7: P-channel Mobility vs.. Here the 0 Volt data imply annealing was carried out with no bias prior to measurement, as in Table 3. P--channel devices displayed more metastability than n-channel devices, that is to say, device characteristic values in p-channel devices did not readily return to initial values after 0 V bias annealing as did n-channel devices after stress testing. References [1] Sze, S. M. Physics of Semiconductor Devices, 2nd Edition. John Wiley & Sons Ltd., New York, [2] Street, R. A. Hydrogenerated Amorphous Silicon. Cambridge University Press, Cambridge, [3] The Fabrication and Characterisation of Hydrogenated Amorphous Silicon Thin Film Transistors (a-si:h TFTs). Engineering Department/ MESP Handout. Cambridge University, [4] Sze, S. M. Semiconductor Devices: Physics and Technology. John Wiley & Sons Ltd., New York,