Crystallization of Amorphous Silicon Using Xenon Flash Lamp Annealing
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1 Crystallization of Amorphous Silicon Using Xenon Flash Lamp Annealing Henry Hellbusch 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 1
2 Purpose Thin Film Transistors (TFT) on glass are utilized for displays Low process temperatures required due to glass Transistor performance affects important display characteristics High mobility impacts refresh rate. Allows for smoother motion for rapidly changing scenes Low leakage currents affects amount of power required to keep a display on A-Si (amorphous silicon), Low Temperature Polysilicon (LTPS with Excimer laser), and IGZO (Indium Gallium Zinc Oxide) are currently the main materials for display transistors LTPS want to minimize grain boundaries 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 2
3 Previous Results Bulk film (not patterned) does not result in macro crystals Importance of TEOS capping layer Observed proximity effect to street [2] 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 3
![layer Observed proximity effect to street [2]](/docs-images/42/20150581/images/page_3.jpg "2/5/2016 RIT - Corning - Crystallization of A-Si")
4 Crystallization Theory Edges of mesa act as seed for grain propagation Border around mesa Regimes of crystallization nano, micro and macro Nano - pink on edges Micro - Light blue Macro the rest of it Adjusted color curves Original colors 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 4
5 Process Flow Glass substrate from Corning Deposit PECVD amorphous silicon (thickness target 60 nm) Dehydrogenation via furnace Out diffusion of hydrogen - uncontrolled dehydrogenation can cause blistering Pattern the a-si layer Deposit oxide (TEOS) as a capping layer Pre-heat Substrate (525 C) & Expose to Xenon flash lamp 19 kw/cm 2 30 kw/cm 2 Single pulse; duration of µsec 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 5
6 Flash Lamp Setup Tool Exposure Spectra NovaCentrix Pulseforge 3300 a-si Absorption Spectra es/pulseforge/samplechart2.png Absorption Coefficient (1/cm) Wavelength (nm) 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 6
7 Flash Lamp Setup Substrate is heated to 525C via hot plate Hot Plate + Substrate placed underneath exposure unit 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 7
8 Mask Design Explore proximity effects Rectangle grids with different gap sizes and rectangle sizes Explore different shapes Triangles (with different angles), squares, rounded edges, octagon, rectangles with fingers 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 8
9 Mask Design Upper left Gradient of varied gap size with 200x100 µm rectangles shotgun spread Large grid of 200x100 µm rectangles with 10 µm gap Intention of x-ray diffraction metrology 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 9
10 Mask Design Upper right Sparse 2:1 rectangles Step size is 20 µm : 10 µm 200x100 µm through 1000x500 µm. 1000x500 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 10
11 Mask Design Lower left Small rectangles of varying size 200x100 bricks with varied gap size 3x3 grid 4x4 grid 4x4 staggered 200x100 brick with varying distance from street Many geometrical shapes of interest 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 11
12 Mask Design Lower right Very large mesas 1000x µm gap Intention of x-ray diffraction 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 12
13 Tool Output Characterization - Bolometer Readings Energy Output of Pulseforge Lamps; Duration= 200 us 550 V, 200 µs (avg) 5.32 J/cm 2 (std dev) Energy [J/cm 2 ] Voltage 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 13
14 Experiment Order Name Treatment Voltage Duration 1 1F Vacuum Anneal F Furnace Anneal E Furnace Anneal D Furnace Anneal D Vacuum Anneal E Vacuum Anneal Naming Conventions: 1 Vacuum Anneal (oven) 2 Furnace Anneal F 580 Volts E 590 Volts D 600 Volts 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 14
15 1F - Grids Vacuum Anneal, 580 Volts, 200 µs Dark field images 200x gap 200x gap 200x gap 200x100 2 gap 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 16
16 1F - Grids Vacuum Anneal, 580 Volts, 200 µs Dark field images Distinct change in border size as mesa exits brick pattern 200x100 2 gap 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA x100 5 gap
17 1F Vacuum Anneal, 580 Volts, 200 µs Clear field images Rounded or triangular end result in about the same amount of usable area Tiling with rounded or triangular mesas may result in better performance 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 18
18 1F Vacuum Anneal, 580 Volts, 200 µs Clear field images Able to fully crystalize the stepped bar Stitched image 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 19
19 2F Furnace Anneal, 580 Volts, 200 µs Clear field images 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 20
20 2F Furnace Anneal, 580 Volts, 200 µs Clear field images 200x100 2 gap 200x100 5 gap 200x gap 1000x500, isolated (1 x 0.5 mm) 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 21
21 2E Furnace Anneal, 590 Volts, 200 µs Clear field images 200x100 mesas Some macro on large grid 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 22
22 2E Furnace Anneal, 590 Volts, 200 µs Clear field images 200x100 2 gap 200x100 5 gap 200x gap 200x gap 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 23
23 2D Furnace Anneal, 600 Volts, 200 µs Clear field images 200x100 2 gap 200x100 5 gap 200x gap 200x gap 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 24
24 1D - Grids Vacuum Anneal, 600 Volts, 200 µs Clear field images 200x100 2 gap 200x100 5 gap 200x gap 200x gap 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 25
25 Results - Summary Grids Reducing gap size reduces border size Large grids did not form macro crystals an upper limit of the size of grid before needing a large gap Isolated Mesa 500x1000 µm mesa forms macro with little random nucleation Long Bar Macro crystals on ends Too long? Too close to large grid of mesas? Furnace annealed samples show more macro grain formation Hydrogen content has an effect (verification via SIMS needed) 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 26
26 Acknowledgements Dr. Cormier (PulseForge system) Robert Corning Inc. Senior Class Dr. Pearson & Dr. Ewbank SMFL Staff Team Eagle & Dr. Hirschman Chris Reepmeyer Karthik Bhadrachalam Tarun Mudgal Nick Edwards 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 27
27 References [1] Ohdaira, K., Endo, Y., Fujiwara, T., Nishizaki, S., and Matsumura, H., Formation of highly uniform micrometer-order-thick polycrystalline silicon films by flash lamp annealing of amorphous silicon on glass substrates, Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications Review Papers 46 (12), (2007). ISI Document Delivery No.: 243WV Times Cited: 30 Cited Reference Count: 16 Ohdaira, Keisuke Endo, Yohei Fujiwara, Tomoko Nishizaki, Shogo Matsumura, Hideki 30 Inst pure applied physics Tokyo Physics, Applied. [2] Saxena, S. and Jang, J., Protrusions of super grains formed by ultrashort xe flash-lamp annealing of amorphous silicon and its effect on the performances of thin-film transistors, Ieee Transactions on Electron Devices 58 (8), (2011). ISI Document Delivery No.: 805EF Times Cited: 2 Cited Reference Count: 23 Saxena, Saurabh Jang, Jin Ministry of Knowledge Economy of the Korean government [F ] This work was supported by the Information Display RD Center, which is one of the Knowledge Economy Frontier RD Program funded by the Ministry of Knowledge Economy of the Korean government under Grant F The review of this paper was arranged by Editor H.-S. Tae. 2 Ieee-inst electrical electronics engineers inc Piscataway Si Engineering, Electrical Electronic; Physics, Applied. [3] Saxena, S., Kim, D. C., Park, J. H., and Jang, J., Polycrystalline silicon thin-film transistor using xe flash-lamp annealing, Ieee Electron Device Letters 31 (11), (2010). ISI Document Delivery No.: 670ST Times Cited: 7 Cited Reference Count: 12 Saxena, Saurabh Kim, Dong Cheol Park, Jeang Hun Jang, Jin MKE/KEIT, Korea [KI002182] This work was supported by the IT RD program of MKE/KEIT (KI002182, TFT Backplane Technology for Next-Generation Display), Korea. The review of this letter was arranged by Editor J. K. O. Sin. 7 Ieee-inst electrical electronics engineers inc Piscataway Engineering, Electrical Electronic 2/5/2016 RIT - Corning - Crystallization of A-Si with FLA 28
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