NAND Flash memory. Samsung Electronics, co., Ltd Flash design team Kihwan Choi - 1/48 - ELECTRONICS

Transcription

1 NAND Flash memory Samsung Electronics, co., Ltd Flash design team Kihwan Choi - 1/48 -

2 Contents Introduction Flash memory 101 Basic operations Current issues & approach In the near future - 2/48 -

3 NAND Flash Application SSD DMB phone E-Book PMP DVD player Telematics Portable Internet Compute r Game ~1999 Serve PC Oriented Mobile DSC PDA r MP3 Digital TV Digital Camcorder -Smart phone 1GB -MP3 Player 4GB -UFD 2GB -DSC 2GB -GAME 1GB -Note book 2GB 1GB -Camcorder 8GB -Smart phone 32MB -MP3 Player 128MB -UFD 256MB -DSC 128MB -Note book 512MB - 3/48-20GB GB Mobile & Consumer Oriented 2010

4 Flash memory in Wikipedia Flash memory is a non-volatile computer storage technology that can be electrically erased and reprogrammed. Flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate : several transistors are connected in series, and only if all word lines are pulled high (above the transistors' VT) is the bit line pulled low. - 4/48 -

5 Flash memory in Wikipedia To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed. NAND flash uses tunnel injection for writing and tunnel release for erasing. One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a "block" at a time. Another limitation is that flash memory has a finite number of erase-write cycles. Most commercially available flash products are guaranteed to withstand around 100,000 write-erase-cycles, before the wear begins to deteriorate the integrity of the storage - 5/48 -

6 Flash memory in Wikipedia Technology scaling down Reference: EETimes article on NAND scaling, 3/22/2010-6/48 -

7 Major players - 7/48 -

8 Now in the market Intel, Micron and IMFT announce world s first 25-nm NAND technology February 2, 2010, By Sanjeev Ramachandran in Hardware The NAND flash production scene has received a shot in the arm with Intel Corporation and Micron Technology making it public that the world s first 25-nanometer (nm) NAND technology is now on stream. Significantly enough, the 25nm process is the smallest NAND technology as well as the smallest semiconductor technology in the world Hynix Develops 26nm NAND Flash Memory Tuesday, February 09, 2010 South Korea's Hynix Semiconductor Inc., the world's second-largest memory chipmaker, said Tuesday that it has developed a 26- nanometer based NAND flash memory chip. The company is the world's second flash memory maker to apply the below 30-nanometer technology. Mass production of the new memory will start in in July. Toshiba readies sub-25nm flash memory chip production By Jose Vilches, TechSpot.com Published: April 5, 2010, 12:14 PM EST The company produces 32nm and 43nm memory chips, but the plan is to begin production on "sub-25nm" chips that would enable larger storage capacities to be shoved into the same form factors that we use today. Toshiba will begin output of NAND chips with circuitry widths in the upper 20 nanometre range soon, while production of chips with circuitry widths in the lower 20 nanometres is slated to start as early as Samsung pioneers 20-nm NAND flash memory technology April 19, 2010, By Thomas Antony in Storage Right on the heels of Toshiba s announcement to start on sub-25nm flash memory, Samsung today announced the industry s first production of 20 nanometer class NAND chips for use in SD cards. Samsung s 20nm MLC 32-gigabit NAND chips are sampling now for use in embedded storage and SD memory cards ranging from 4GB to 64GB. This is a significant step forward for Samsung who started its 30nm production just one year ago. The new class of memory chips will allow for higher-density in storage, lower manufacturing costs and 50% higher productivity than 30nm technology. - 8/48 -

9 Flash memory 101-9/48 -

10 Flash memory cell vs. MOSFET Flash cell has a charge storage layer such that Vth of a cell can be changed memorize information G Charge storage G S F/G D S D n n n n p p B B Flash cell MOSFET - 10/48 -

11 Flash memory operation Write & read binary data to a flash cell data 0 OFF state (program) data 1 ON state (erase) MOS Transistor Vg(Vg>Vth1) No. of cells Read Program Vs(0V) Vth1 ON Vd(>0V) Ids1(>0) Erase Vg(Vg<Vth2) ON OFF OFF Vth [V] Vs(0V) Vth2 Vd(>0V) Ids2(=0) - 11/48 -

12 Flash memory cell structure Cell Vth changes depending on the amount of F/G charge electrons can be injected(ejected) into(out of) the F/G through Tox with electric field across Tox B/L Metal Dielectric : ONO Source C/G(W/L) F/G(F-Poly) Drain Charge Storage Node Tunnel Ox - 12/48 -

13 - 13/48 - NAND vs. NOR Logic gate A B C A B C Truth table B 0 0 C A B 1 0 C A NAND NOR circuit C A A B B C A A B B Flash

14 Features : NAND vs. NOR - 14/48 -

15 Write methods in Flash memory Hot Electron Injection Fowler-Nordheim Tunneling Program in NOR Flash Impact ionization at drain side Program/Erase in NAND Flash Erase in NOR Flash - 15/48 -

16 NAND Flash : Program & Erase Vcg = 18 V Vcg = 0V 0V e e e e 0V float e e e e float Vsub = 0V Vsub = 20V Program F-N Tunneling Off cell (Solid-0) Erase F-N Tunneling On cell (Solid-1) - 16/48 -

17 Coupling ratio C/G Vfg = Vcg α cg F/G CONO α cg = CONO (CD+CS+CB+CONO) CS Source CB CD Drain α cg : Coupling Ratio (From Q=CV and Charge Conservation Law) For fast programming, high Vfg is required, i.e. either high Vcg or large α cg - 17/48 -

18 NAND Flash cell structure BL DC Active SSL WL SSL WL Gate F-Poly ONO Tunnel Ox F-Poly WL Direction Gate F-Poly ONO GSL CSL GSL CSL PP-Well BL Direction Tunnel Ox Schematic Top View Vertical View - 18/48 -

19 Terms in NAND Flash string, page, block string : minimum cell array element page : program unit block : erase unit - 19/48 -

20 NAND Flash chip architecture High density & simple architecture (cell efficiency > 65%) Control I/O Pad WL Decoder & Driver Memory Array Memory Array Memory Array Memory Array Block = 128-page (2Mb~4Mb) SLC : 64-page MLC : 128-page Samsung 63nm 8Gb MLC NAND - 20/48 - Page Driver & Buffer (2KB~4KB) Peripheral & Charge Pump Data I/O Pad

21 Functional block diagram of NAND Flash A12~A30 A0~A11 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders X - D E C. Cell Array Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver I/O 0 I/O 7 CLE ALE WP - 21/48 -

22 Basic operations NAND Flash - 22/48 -

23 Read operation Bias condition - selected WL : Target voltage (Vtarget) - unselected WLs : high enough to conduct all cells in a string 1V SSL Vread Unselected WLs Selected WL Vread Vread Vtarget Vtarget Vread Vread Unselected WLs Vread Vread P1 P2 Vth Vread Vread GSL Vread 0V - 23/48 -

24 Sensing margin The ratio of On cell & Off cell current Precharge Level (Vp) Off cell Sensing margin Sensing Level 0V On cell Precharge Sensing - 24/48 -

25 Read disturbance Increasing Vread soft program occurs in the unselected cell of selected string Vread Vread Vread # of cell Vread Vtarget Vread on 0V Vth Vread Vread Vread Vread Vread On cell moves to off cell - 25/48 -

26 Program operation Bias condition - selected WL : Program voltage (Vpgm) - unselected WLs : Pass voltage (Vpass) Vcc 0V Vcc SSL Unselected WLs Selected WL Unselected WLs GSL Vcc Vpass Vpass Vpgm Vpass Vpass Vpass Vpass Vpass GND # of cell on off 0V Vth on cell becomes off cell - 26/48 -

27 Program inhibition Should not be programmed (= program inhibited) Vcc 0V Vcc Vcc 0V Vpgm Self boosting Vcc Vpass Vcc OFF Vcc-Vth+α Vpass Vpgm GND Vpass Vcc Vpass Vpgm Vpass Vpass Vpass Vpass GND Vcc OFF GND For inhibition only, the higher Vpass, the better Vpgm disturbance But, higher Vpass causes more Vpass disturbance - 27/48 -

28 Self boosting SSL WL31 WL30 WL29 WL28 WL1 WL0 GSL Inhibit BL : Vcc Vcc 10V 10V 20V 10V 10V 10V 0V Bias sequence for self boosting Vpgm Vpass Inhibit channel is boosted!!! Program channel Channel potential strongly depends on the cell states in a string - 28/48 -

29 Vpass window Optimal Vpass region considering both Vpgm and Vpass disturbances at the same time Program cell 0V Inhibit cell VCC SSL VCC Vpass Window Curve WL31 WL30 WL29 10V 10V 20V Vth Vpgm disturbance Vpass disturbance WL28 10V -1V WL1 10V WL0 10V Vpass GSL 0V Vpass window Vchannel = 0V Vchannel = 8~9V - 29/48 -

30 Bias condition - all WLs in the selected Block : 0V - GSL/SSL : Floating - Bulk : Vera Erase operation Floating GND GND GND GND on # of cell 0V off Vth GND GND GND GND Floating off cell becomes on cell - 30/48 -

31 Erase disturbance Self boosting can be used Old Method New Method B/L (20V) B/L (20V) SSLn(20V) SSLn(Floating) Select Block WL0(0V) Select Block WL0(0V) WL7(0V) WL7(0V) GSLn(20V) GSLn(Floating) CSL(20V) CSL(20V) Unselect Block GSLn-1(20V) WL7(20V) Unselect Block GSLn-1(Floating) WL7(Floating) WL0(20V) WL0(Floating) SSLn-1(20V) SSLn-1(Floating) Cell Array Substrate 0V 20V Cell Array Substrate 0V 20V - 31/48 -

32 Cell Vth width requirement - 1bit/cell vs. 2bit/cell vs. 3bit/cell Cell Vth distribution # of cells 2 Level Cell Vth Upper Limit SLC E P ( NAND Flash) 4 Level Cell Vread MLC E P1 P2 P3 8 Level Cell 3bit E P1 P2 P3 P4 P5 P6 P7 0V Vth - 32/48 -

33 Cell Vth width control Incremental Step Pulse Program (ISPP) - programmed state Vth width can be controlled - narrower width requires more program loop Change of cell Vth : slow vs. fast cell Cell Vth Vpgm Vvfy Vpgm No. of Loop Vpgm_start - 33/48 -

34 Current issues & approaches - 34/48 -

35 Criteria for a NAND Flash device NAND MLC Vread E P1 P2 P3 Cost Chip size Bit density etc Performance Program time Read time etc Reliability Data retention Program/Read cycle etc All these are strongly dependent on each other and may become worse as cell size shrinks down - 35/48 -

36 Details on programmed Vth Factors which affect to programmed Vth width - Ideal :ΔVpgm during ISPP program - Noise : F-poly coupling, CSL noise, Back pattern dependency - Reliability : Endurance, program/read disturbance, charge loss # of Cells Charge Loss : HTDR, RTDR F-poly coupling Program disturbance Read disturbance Endurance Ideal 0V Verify level Vth - 36/48 -

37 Neighborhood interference F-poly coupling noise - Cell Vth can be raised as neighboring cells are programmed 1 C-poly ONO C-poly ONO Victim 1 P-well Aggressor BL(1) BL(2) BL(3) WL(i+1) WL(i) Vth - 37/48 -

38 Cell Vth vs. F-poly coupling InitialWL BL Diag. Final WL1 Diag. WL Diag. WL2 BL V BL WL3 Diag. WL Diag. Cell State # of cells BL1 BL2 BL3 E P1 P2 P3 Vth - 38/48 -

39 Cell size vs. F-poly coupling 09 ISSCC - 39/48 -

40 F-poly coupling reduction (I) Shadow program - Make final Vth after being coupled Shadow sequence 7 4 WL3 Convential sequence 6 5 WL3 LSB # of cells E P WL2 WL1 LSB # of cells E P WL2 WL1 cell Vth cell Vth MSB # of cells E P1 P2 P3 MSB # of cells E P1 P2 P cell Vth cell Vth - 40/48 -

41 F-poly coupling reduction (II) Reprogram - Make final Vth after being coupled coupled WL # of cells WL Coarse program WL & coupled E P1 P2 P3 cell Vth Fine program where P1 < P1, P2 < P2, P3 < P3 Fine program E P1 P2 P3 cell Vth Program performance overhead due to Fine program - 41/48 -

42 F-poly coupling reduction (III) All-bit line (ABL) architecture - all cells in a WL are programmed at the same time - in SBL, cells in even BL first, cells in odd BL next (BL-coupling exists) SBL(Shielded-bit line) ABL(All-bit line) Physical 8KB cells BLe BLo BL1 BL2 64 cells (one string) One block PB Features : SBL vs. ABL PB PB PB SBL ABL No. of PBs (page depth) 4KB 8KB pages/block 256 pages 128 pages - 42/48 -

43 In the near future - 43/48 -

44 3D Flash memory Bit-Cost Scalable(BiCS) technology 2007 IEDM, Toshiba - 44/48 -

45 3D Flash memory TCAT(Terabit Cell Array Transistor) technology 2009 VLSI, Samsung - 45/48 -

46 What is CTF? CTF (Charge Trap Flash) - SONOS type Flash - electron is trapped in nitride trap layer SONOS Si (S) Oxide (O) Nitride (N) Oxide (O) n + n + P.C.Y. Chen, TED, V. 24, pp , 1977 Floating Gate Si F-Gate Oxide (O) F.Masuoka (Toshiba) IEDM 1984 ON O n + n /48 -

47 Floating gate vs. SONOS No neighborhood coupling All stored charge is lost Thicker tunnel oxide Device Scaling is difficult Only part of the charge is lost Thinner tunnel oxide Device Scaling is easy - 47/48 -

48 Thanks for your listening! - 48/48 -