Lezioni di Tecnologie e Materiali per l Elettronica
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1 Lezioni di Tecnologie e Materiali per l Elettronica Danilo Manstretta [email protected] microlab.unipv.it
2 Outline Passive components Resistors Capacitors Inductors Printed circuits technologies Materials and fabrication steps Assembling Monolithic IC technologies Fabrication steps (thermal oxidation, thermal diffusion, ) IC technologies (CMOS, BiCMOS) Packaging and Thermal Design Lezioni di Tecnologie e Materiali per l'elettronica 2
3 Semiconductor Technologies Point-contact Ge transistor, 1948 J. Bardeen, W. Brattain, W. Shockley (Bell Labs) Integrated Circuit, 1958 J. Kilby (Texas Instruments) Silicon Integrated Circuit, 1961 R. Noyce (Fairchild Semiconductor) Lezioni di Tecnologie e Materiali per l'elettronica 3
4 Planar IC Technologies Jack Kilby and Texas Instruments received U.S. patent #3,138,743 for miniaturized electronic circuits. Robert Noyce and the Fairchild Semiconductor Corporation received U.S. patent #2,981,877 for a silicon based integrated circuit. Lezioni di Tecnologie e Materiali per l'elettronica 4
5 Moore Law (1965) G. Moore prediction, 1965 Actual data N(y+n) = N(y) 2 n Annual doubling Complexity (measured as number of transistors) of the most complex ICs G. Moore, Plenary talk, ISSCC 2003 Lezioni di Tecnologie e Materiali per l'elettronica 5
6 Moore Law (1975) G. Moore prediction, 1975 Actual data N(y+n) = N(y) (1+k) n Memories k~0.5 Logic k~0.35 Two-year doubling Complexity (measured as number of transistors) of the most complex ICs G. Moore, Plenary talk, ISSCC 2003 Lezioni di Tecnologie e Materiali per l'elettronica 6
7 Wafer Size How many transistors can we process together? Lezioni di Tecnologie e Materiali per l'elettronica 7
8 Batch Processing 12 inches wafer ~ 700cm 2 50 wafer shuttle contains ~ dice Lezioni di Tecnologie e Materiali per l'elettronica 8
9 Introduction to IC Technologies Semiconductor materials Wafer fabrication process Production steps: Thermal oxidation Thermal diffusion Ion implantation Thin film deposition Epitaxial growth Lithography MOS transistors Bipolar transistors Integrated Circuit (Physical layout) Integrated Circuit (Die photograph) Lezioni di Tecnologie e Materiali per l'elettronica 9
10 Active Devices CMOS Technology Bipolar Technology Drain Collector Gate Bulk Base Source Emitter Lezioni di Tecnologie e Materiali per l'elettronica 10
11 MOS Capacitance Physical Layout (Cross section) Equivalent Circuit Poly-Si ( Capacitance TOP metal ) p sub G B n+ Gate oxide Capacitance BOTTOM plate C C ox WL Tecnologie e Materiali per l'elettronica 11
12 Resistors Well resistors ~200W/sq sheet resistance High parasitic capacitance Non-linear resistance n+ n+ N well p sub Poly resistors ~200W/sq sheet resistance Linear resistance Field oxide poly p sub Tecnologie e Materiali per l'elettronica 12
13 Technology Cross-Section Metal stack in a recent CMOS technology Cu and Al interconnect Inter-layer VIA holes 11 ox F / m 12 o F / m 10 Si F / m 7 Cu S / m m /Vs Tecnologie e Materiali per l'elettronica 13
14 Passive Devices Thick Metal Thick Metal Capacitance TOP metal Cu Cu High-K Dielectric Capacitance BOTTOM metal Metal-Insulator-Metal (MiM) capacitor ( C u ~2-5fF/m 2 ) Center-Tapped Inductor inductance < ~15nH ) Tecnologie e Materiali per l'elettronica 14
15 MiM Capacitors Capacitance TOP metal Thick Metal Cu Thick Metal Cu C bottom B R s L C T C top High-K Dielectric Capacitance BOTTOM metal S MiM capacitor Physical layout (cross section) Equivalent circuit TOP DIELECTRIC BOTTOM substrate Device parasitics Tecnologie e Materiali per l'elettronica 15
16 MiM Caps: Self-Resonance CROSS SECTION T B T B TOP VIEW capacitive Inductive (parasitic) Z HIGHER SELF- RESONANCE FREQUENCY LOWER SELF- RESONANCE FREQUENCY T T w sr Log w B B Tecnologie e Materiali per l'elettronica 16
17 MOSFET Operation W V KT N DS I D ncoxv GS VTH V DS L A B ln 2 q ni V TH V FB 2 B 4qN C A ox S B C ox t ox ox C gs Vds0 C ox WL SOURCE GATE DRAIN n i = cm -3 at 300K Lezioni di Tecnologie e Materiali per l'elettronica 17
18 Monolithic Silicon Si Atomic density: cm -3 Silicon Properties at 300K R a 1,18Å r 11,7 ( SiO 2 r 3,9 ) E g 1,12eV T f 1412 C TH 1,5 W/Kcm Lezioni di Tecnologie e Materiali per l'elettronica 18
19 Mobility and Conductivity Generic Si: J drift E N-type Si: qn n qp E p n N p D n N 2 i J E qn E D drift D n P-type Na=10 14 cm -3 r=150 W cm Na=10 19 cm -3 r=9m W cm Lezioni di Tecnologie e Materiali per l'elettronica 19
20 Sheet Resistance I V R L r Wt R L W R =r/t Lezioni di Tecnologie e Materiali per l'elettronica 20
21 Scaling and Time Delay C gs Vds0 C ox WL L L Rr R Wt W L R CoxWL R CoxL W 2 Scaling of device size leads to shorter time delay and higher (maximum) operating frequency! Lezioni di Tecnologie e Materiali per l'elettronica 21
22 HOW INTEGRATED CIRCUITS ARE MADE IC PROCESS FLOW Lezioni di Tecnologie e Materiali per l'elettronica 22
23 Si Wafer Fabrication Wafer size Diameter 8-12 inches Thickness 300m-1.2mm Lezioni di Tecnologie e Materiali per l'elettronica 23
24 Si Wafer Fabrication During wafer production a controlled amount of impurity (dopant) is inserted together with silicon Typically p-type impurity (e.g. Boron) for CMOS processes Lezioni di Tecnologie e Materiali per l'elettronica 24
25 Thermal Oxidation Creates a thin silicon di-oxide (SiO 2 ) dielectric layer of excellent quality Thermally grown SiO 2 is used as: Gate oxide in MOS transistors (~25Å in 90nm CMOS) Isolation between substrate and metal layers (field oxide) Mask for doping diffusion SiO 2 Original Si surface substrate p Lezioni di Tecnologie e Materiali per l'elettronica 25
26 Thermal Oxidation Setup Wet oxidation Oxide growth Lezioni di Tecnologie e Materiali per l'elettronica 26
27 Arrhenius Law Like may other chemical reactions, thermal oxidation is governed by Arrhenius law. Reaction speed varies exponentially with temperature: C 0 C e E A KT K = J/K = ev/k E A = 1.18 ev (dry oxidation:o 2 ) E A = 0.79 ev (wet oxidation: H 2 O) Temperature dependence of reaction speed. Example: speed at 1100 C speed at 100 C 0.1m per hour m per hour Need for a very accurate temperature control! Lezioni di Tecnologie e Materiali per l'elettronica 27
28 Thermal Diffusion Introduces a controlled amount of impurities (dopant) in the area directly below the surface (n/p-well for contact, isolation, etc.) Impurities substitute Si atoms N-type (donor atoms): As, P, Sb P-type (acceptor atoms): B Misfit Factor = R A,sub / R A,Si Lezioni di Tecnologie e Materiali per l'elettronica 28
29 Dopant Diffusion Steps Predeposition Dopant gas: PH 3, AsH 3, B 2 H 6 Doping elements are introduced in a shallow region beneath the surface Drive-in Doping elements diffuse inside the substrate. Thermal diffusion setup is similar to thermal oxidation setup. The process is controlled by the reaction temperature. Lezioni di Tecnologie e Materiali per l'elettronica 29
30 Dopant Profiles: Drive-in Peak doping concentration is always at the Si surface Constant source diffusion (predeposition) Doping is carried out on an already doped Si substrate A p-n junction is formed at a certain depth below the surface: junction depth JUNCTION DEPTH Lezioni di Tecnologie e Materiali per l'elettronica 30
31 Doping profiles limited precision Further thermal cycles alter the dopant profiles Diffusion takes place in two dimensions: lateral diffusion limits planar selectivity as a function of doping depth Diffusion Mask Lezioni di Tecnologie e Materiali per l'elettronica 31
32 Ion Implantation Introduces a well controlled amount of dopant in the substrate Can be a substitute for thermal diffusion or just for predeposition Must be followed by a thermal cycle (annealing) to repair damages Lezioni di Tecnologie e Materiali per l'elettronica 32
33 Ion Implantation F q v B Lezioni di Tecnologie e Materiali per l'elettronica 33
34 Technology Cross-Section Metal layers stack in a recent CMOS technology Cu and Al interconnect Inter-layer VIA holes Lezioni di Tecnologie e Materiali per l'elettronica 34
35 Passive Devices Metal-Insulator-Metal (MiM) capacitor Center-Tapped Inductor Thick Metal Thick Metal Capacitance TOP metal Cu Cu High-K Dielectric Capacitance BOTTOM metal Lezioni di Tecnologie e Materiali per l'elettronica 35
36 Thin Film Deposition METAL LAYERS STACK Important parameters: Uniformity: constant layer thickness Processing temperature Cost per wafer Step coverage Lezioni di Tecnologie e Materiali per l'elettronica 36
37 Thin Film Deposition Conductive layers: Al, Cu, poly-si, W, other metals Dielectric layers: SiO 2, silicon nitride (Si 3 N 4 ) Lezioni di Tecnologie e Materiali per l'elettronica 37
38 Chemical Vapor Deposition (CVD) 1. The chemical reaction of one or more gas compounds creates the desired material in gas (vapor) form. 2. A thin film of material is formed through deposition from vapor state. 3. Substrate heating enhances the chemical reaction, accelerating the deposition process (Temperatures up to 1000 C) 4. Alternatively plasma can be used to enhance reaction (plasma enhanced CVD) at moderate temperatures (up to 400 C) There are three main types: Atmospheric-pressure CVD Low-pressure CVD (LPCVD) Plasma enhanced CVD (PECVD) Water cooled chamber Wafer Gas Heater Quarz Reactor Lezioni di Tecnologie e Materiali per l'elettronica 38
39 Physical Vapor Deposition (PVD) 1. The atoms of the material to be deposed reach high kinetic energy in a vacuum chamber 2. Thanks to vacuum condition, atoms reach the substrate (target) with few or no collisions 3. A thin layer with crystalline structure is formed Lezioni di Tecnologie e Materiali per l'elettronica 39
40 PVD: Evaporation Joule heating Filament Electron beam The desired material is vaporized through heating in a vacuum chamber Joule heating, electron beam, pulsed laser beam, filament evaporation (current), flash evaporation Lezioni di Tecnologie e Materiali per l'elettronica 40
41 PVD: Sputtering I V B (~kv) - + Al target DC plasma Al Ar+ Ar+ Al Ar plasma Deposited Al film Wafer Plasma is a low pressure gas where a high energy electric field is used to drive ionization creating a large number of ions and free electrons Fine particles of the desired material are ejected from a solid target by applying plasma excitation Lezioni di Tecnologie e Materiali per l'elettronica 41
42 Vapor Phase Epitaxy (VPE) * It is a type of CVD where the deposed layer (epitaxial layer) has crystalline structure High temperature ( C) is required Dopant is added in the reaction chamber during deposition Si epi layer SiCl H Si 4HCl Si - Substrate * Crescita epitassiale Lezioni di Tecnologie e Materiali per l'elettronica 42
43 Expitaxial Layer Uniform doping concentration Abrupt doping concentration step Higher mobility compared to doping through overcompensation Autodoping: impurities in the reactor atmosphere alter doping in the epitaxial layer Outdiffusion: impurities in the Si wafer diffuse into the epitaxial layer Buried layers alter the shapes in the epitaxial layer Lezioni di Tecnologie e Materiali per l'elettronica 43
44 Lithographic Process Design Mask Wafer Lezioni di Tecnologie e Materiali per l'elettronica1 44
45 Lithographic Process Resist application Soft bake Exposure Develop Cycle Hard baking Etching Lezioni di Tecnologie e Materiali per l'elettronica 45
46 Resists for Lithography Photo-resists are composite materials made of: Organic polymer Photoactive compound Solvent (eliminated during soft-bake) Positive resist Higher resolution Negative resist Lower resolution Lezioni di Tecnologie e Materiali per l'elettronica 46
47 Photolithographic Masks Masks set Mask making: electron beam lithography (step and repeat) Each mask includes: Alignment marks Mask making patterns Cr, Cr 2 O 3, Fe 2 O 3, Process monitor patterns quartz Lezioni di Tecnologie e Materiali per l'elettronica 47
48 Mask Making Electron beam lithography Resist activated directly by directive electron beam, without mask Resolution < 1nm Very low throughput (very high cost) Lezioni di Tecnologie e Materiali per l'elettronica 48
49 Printing Techniques Techniques: Contact Proximity Projection Exposure of a portion of the wafer (low throughput) High resolution (depends on l) Requires excellent planarity of the wafer for proper focusing Lezioni di Tecnologie e Materiali per l'elettronica 49
50 Step and Repeat WAFER STEPPER Exposition carried out on a limited area (field), then wafer is repositioned and exposition is repeated on an adjacent area Focus and alignment after each step low throughput De-magnification: 4-10:1 Excellent chip resolution: better than mask resolution Lezioni di Tecnologie e Materiali per l'elettronica 50
51 Chemical Mechanical Polishing - CMP Elastic film Thick dielectric film deposition Wafer is polished using abrasives and etching agents Enhanced local and long range planarity Lezioni di Tecnologie e Materiali per l'elettronica 51
52 References Reading Material: Dispense di G. Torelli. Introduzione alla tecnologia dei circuiti integrati su silicio (IC Technologies) Dispense del corso Microfabrication Technology, UCB Tecnologie e Materiali per l'elettronica 52
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