Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

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1 Lecture 030 DSM CMOS Technology (3/24/10) Page LECTURE DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron CMOS technology Summary CMOS Analog Circuit Design, 2 nd Edition Reference New material Lecture 030 DSM CMOS Technology (3/24/10) Page CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGY of Transistors The use of reverse bias pn junctions to isolate transistors becomes impractical as the transistor sizes decrease.

2 Lecture 030 DSM CMOS Technology (3/24/10) Page Use of Technology trench isolation (STI) allows closer spacing of transistors by eliminating the depletion region at the surface. Salicide Well Salicide Decreased spacing p+ p+ Salicide Oxide p+ p p- n- n Poly Salicide Polycide Metal Lecture 030 DSM CMOS Technology (3/24/10) Page Comparison of STI and LOCOS What are the differences between a LOCOS and STI technology? Comments: If the n + to p + spacing is large, the Bird s beak can be compensated using techniques such as poly buffered LOCOS At some point as the n + to p + spacing gets smaller, the restricted bird s beak leads to undesirable stress effects in the transistor. An important advantage of STI is that it minimizes the heat cycle needed for n + or p + isolation compared to LOCOS. This is a significant advantage for any process where there are implants before STI.

3 Lecture 030 DSM CMOS Technology (3/24/10) Page (STI) 1.) Cover the wafer with pad oxide and silicon nitride. 2.) First etch nitride and pad oxide. Next, an anisotropic etch is made in the silicon to a depth of 0.4 to 0.5 microns. (1) (2) Nitride Silicon 3.) Grow a thin thermal oxide layer on the trench walls. (3) 4.) A CVD dielectric film is used to fill the trench. (4) 5.) A chemical mechanical polishing (CMP) step is used to polish back the dielectric layer until the nitride is reached. The nitride acts like a CMP stop layer. 6.) Densify the dielectric material at 900 C and strip the nitride and pad oxide. (5) (6) Lecture 030 DSM CMOS Technology (3/24/10) Page Illustration of a Deep Submicron (DSM) CMOS Technology Polycide Salicide STI NMOS Transistor ;; Source/drain extensions Deep Sidewall Spacers Salicide STI PMOS Transistor p+ ; p+ Source/drain extensions Deep Metal Layers 0.8μm M8 M7 M6 Polycide M5 0.3μm M4 Salicide M3 M2 M1 STI p-substrate 7μm In addition to NMOS and PMOS transistors, the technology provides: 1.) A deep that can be utilized to reduce substrate noise coupling. 2.) A MOS varactor that can serve in VCOs 3.) At least 6 levels of metal that can form many useful structures such as inductors, capacitors, and transmission lines.

4 Lecture 030 DSM CMOS Technology (3/24/10) Page Transistors f T as a function of gate-source overdrive, V GS -V T (0.13μm): 70 Typical, 25 C ft (GHz) NMOS PMOS Slow, 70 C Typical, 25 C Slow, 70 C V GS -V T (mv) The upper frequency limit is probably around 40 GHz for NMOS with an f T in the vicinity of 60GHz with an overdrive of 0.5V and at the slow-high temperature corner. Lecture 030 DSM CMOS Technology (3/24/10) Page Resistors 1.) Diffused and/or implanted resistors. 2.) Well resistors. 3.) Polysilicon resistors. 4.) Metal resistors.

5 Lecture 030 DSM CMOS Technology (3/24/10) Page Capacitors Polysilicon-polysilicon capacitors: Metal-metal capacitors: Protective Insulator Layer Intermediate Oxide Layers Metal Via Capacitor dielectric Capacitor bottom plate Vias connecting bottom plate to lower metal Vias connecting top plate to top metal Capacitor Top Metal Vias connecting bottom plate to lower metal Top Metal Second level from top metal Third level from top metal Fourth level from top metal Lecture 030 DSM CMOS Technology (3/24/10) Page Inductors Top view and cross-section of a planar inductor: W Top Metal Top Metal S Next Level Metal Vias Oxide Next Level Metal D Oxide Silicon D N turns

6 Lecture 030 DSM CMOS Technology (3/24/10) Page TYPICAL DEEP SUBMICRON (DSM) CMOS FABRICATION PROCESS Major Fabrication Steps for a DSM CMOS Process 1.) p and n wells 2.) trench isolation 3.) Threshold shift and anti-punch through implants 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide 10.) Higher level metals, tungsten plugs/vias, and oxide 11.) Top level metal, vias and protective oxide Lecture 030 DSM CMOS Technology (3/24/10) Page Starting Material The substrate should be highly doped to act like a good conductor. Oxide p+ p p- n- n Poly Salicide Polycide Metal

7 Lecture 030 DSM CMOS Technology (3/24/10) Page Step 1 - n and p wells These are the areas where the transistors will be fabricated - NMOS in the and PMOS in the. Done by implantation followed by a deep diffusion. n well implant and diffusion p well implant and diffusion p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal Lecture 030 DSM CMOS Technology (3/24/10) Page Step 2 The shallow trench isolation (STI) electrically isolates one region/transistor from another. p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal

8 Lecture 030 DSM CMOS Technology (3/24/10) Page Step 3 Threshold Shift and Anti-Punch Through Implants The natural thresholds of the NMOS is about 0V and of the PMOS is about 1.2V. An p- implant is used to make the NMOS harder to invert and the PMOS easier resulting in threshold voltages balanced around zero volts. Also an implant can be applied to create a higher-doped region beneath the channels to prevent punch-through from the drain depletion region extending to source depletion region. anti-punch through implant p+ anti-punch through implant p threshold implant p threshold implant Oxide p+ p p- n- n Poly Salicide Polycide Metal Lecture 030 DSM CMOS Technology (3/24/10) Page Step 4 Thin Oxide and Polysilicon Gates A thin oxide is deposited followed by polysilicon. These layers are removed where they are not wanted. p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal

9 Lecture 030 DSM CMOS Technology (3/24/10) Page Step 5 Lightly Doped Drains and Sources A lightly-doped implant is used to create a lightly-doped source and drain next to the channel of the MOSFETs. p- Implant p- Implant n- Implant n- Implant p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal Lecture 030 DSM CMOS Technology (3/24/10) Page Step 6 Sidewall Spacers A layer of dielectric is deposited on the surface and removed in such a way as to leave sidewall spacers next to the thin-oxide-polysilicon-polycide sandwich. These sidewall spacers will prevent the part of the source and drain next to the channel from becoming heavily doped. Sidewall Spacers Sidewall Spacers p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal

10 Lecture 030 DSM CMOS Technology (3/24/10) Page Step 7 Implantation of the Heavily Doped Sources and Drains Note that not only does this step provide the completed sources and drains but allows for ohmic contact into the wells and substrate. implant p+ implant p+ implant implant implant p+ implant p+ p+ p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal Lecture 030 DSM CMOS Technology (3/24/10) Page Step 8 Siliciding (Salicide and Polycide) This step reduces the resistance of the bulk diffusions and polysilicon and forms an ohmic contact with material on which it is deposited. Salicide = Self-aligned silicide Polycide Polycide Salicide Salicide Salicide Salicide p+ p+ p+ Oxide p+ p p- n- n Poly Salicide Polycide Metal

11 Lecture 030 DSM CMOS Technology (3/24/10) Page Step 9 Intermediate Oxide Layer An oxide layer is used to cover the transistors and to planarize the surface. Lecture 030 DSM CMOS Technology (3/24/10) Page Step 10- First-Level Metal Tungsten plugs are built through the lower intermediate oxide layer to provide contact between the devices, wells and substrate to the first-level metal.

12 Lecture 030 DSM CMOS Technology (3/24/10) Page Step 11 Second-Level Metal The previous step is repeated for the second-level metal. Lecture 030 DSM CMOS Technology (3/24/10) Page Completed Fabrication After multiple levels of metal are applied, the fabrication is completed with a thicker toplevel metal and a protective layer to hermetically seal the circuit from the environment. Note that metal is used for the upper level metal vias. The chip is electrically connected by removing the protective layer over large bonding pads.

13 Lecture 030 DSM CMOS Technology (3/24/10) Page Scanning Electron Microscope of a MOSFET Cross-section TEOS Tungsten Plug SOG TEOS/BPSG Polycide Sidewall Spacer Poly Gate Fig Lecture 030 DSM CMOS Technology (3/24/10) Page Scanning Electron Microscope Showing Metal Levels and Interconnect Aluminum Vias Tungsten Plugs Metal 3 Metal 2 Metal 1 Transistors Fig

14 Lecture 030 DSM CMOS Technology (3/24/10) Page SUMMARY DSM technology typically has a minimum channel length between 0.35μm and 0.1μm DSM technology addresses the problem of excessive depletion region widths in junction isolation techniques by using shallow trench isolation DSM technology may have from 4 to 8 levels of metal Lightly doped drains and sources are a key aspect of DSM technology