Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process

Size: px

Start display at page:

Download "Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process"

Arabella Fields
7 years ago
Views:

1 Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

concerning semiconductor and electronics technology, please call Sales at Chipworks.

2 Process Review Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PPR JMRKBT Revision 1.0 Published: July 12, 2010

It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached.

3 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Recessed Wordline 3.8 Isolation 3.9 Wells and Substrate 4 SDRAM Cell Analysis 4.1 Overview 4.2 Cross-Sectional Analysis 4.3 Plan View Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks

4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Recessed Wordline 3.8 Isolation 3.9 Wells and Substrate 4 SDRAM Cell Analysis 4.

4 Overview Overview 1.1 List of Figures 2 Device Overview Top Package View Bottom Package View Package X-Ray (Top View) Package X-Ray (Side View) W971GG6JB-25 Die Die Markings W971GG6JB-25 Die at Metal Analysis Sites Top Left Corner of Die Bottom Right Corner of Die Minimum Pitch Bond Pads Minimum Pitch Test Pads E-Fuses Overview Optical Plan View SDRAM Memory Block 3 Process Analysis General View of W971GG6JB-25 Parallel to Wordline General View of W971GG6JB-25 Parallel to Bitline Die Edge Overview Die Edge Detail Bond Pad Left Bond Pad Edge Passivation SEM Passivation Over Top of Metal 3 Line TEM Passivation Between Narrow Metal 3 Lines TEM IMD IMD 2 Layers IMD PMD Metal 3 TEM Metal 3 Cap TEM Metal 3 Bottom TEM Metal Minimum Pitch Metal 2 TEM Metal 2 Cap TEM Bottom Metal 2 TEM Minimum Pitch Metal 1 SEM Metal 1 in Detail TEM Overview of Via 2, Via 1 and Contact SEM Minimum Width Via Minimum Pitch Via 1 to M Via 1 to M1 TEM

2.6 SDRAM Memory Block 3 Process Analysis 3.1.1 General View of W971GG6JB-25 Parallel to Wordline 3.1.2 General View of W971GG6JB-25 Parallel to Bitline 3.1.3 Die Edge Overview 3.1.4 Die Edge Detail 3.

5 Overview Via 1 to SDRAM Top Electrode Via 1 to SDRAM Top Electrode Planar TEM W Contacts W Contact to Diffusion Contact Bottom TEM Slot Contact to Diffusion Length Slot Contact to Diffusion Interface Bitline Contact Planar TEM Peripheral Transistor Contacts Planar TEM Peripheral Transistor Contacts Planar TEM NMOS Peripheral Transistor PMOS Peripheral Transistor Peripheral Transistor TEM Peripheral Gate TEM Bitline TEM Peripheral Gate Wrap TEM Peripheral Transistor ONO Gate Dielectric TEM Peripheral Transistor Channel Orientation TEM Wordline Transistor Overview Wordline Transistor Detail Wordline Transistor Bottom Detail Wordline Transistor Gate Width Minimum Width STI Peripheral STI Depth Peripheral STI Depth Array Well Structure SEM (Si Stain) Well Structure SCM SDRAM N-Well and P-Well SCM SDRAM N-Well and P-Well SRP Peripheral P-Well and Substrate SRP 4 SDRAM Cell Analysis SDRAM Cross Section (Parallel to Wordline) TEM Top of SDRAM Cells Overview TEM Top of SDRAM Cell TEM Bottom of SDRAM Top Plate TEM DRAM Capacitor Top Plate Extension TEM Top Plate Extension ARC TEM Lower Section of Storage Capacitor TEM Bottom of Storage Capacitor TEM Cell/Poly Plug Contact TEM Cell/Poly Plug Contact TEM Tungsten Wordline Contact TEM Tungsten Bitline Contact TEM Center of Array TEM Cell Contact TEM

1 NMOS Peripheral Transistor 3.6.2 PMOS Peripheral Transistor 3.6.3 Peripheral Transistor TEM 3.6.4 Peripheral Gate TEM 3.6.5 Bitline TEM 3.6.6 Peripheral Gate Wrap TEM 3.6.7 Peripheral Transistor ONO Gate Dielectric TEM 3.

6 Overview Plan-View Analysis Reference Capacitor Near Top TEM (A) Capacitor Cylinders at Their Tops TEM (A) Capacitor Cylinder Composition TEM (A) Capacitor Cylinder Composition STEM (A) Capacitor Cylinders at Bottom of Upper Plate TEM (B) Overview of Capacitor Cylinders in Oxide Support Layer Level TEM (C) Details of Capacitor Cylinders in Oxide Support Layer Level TEM (C) Capacitor Cylinders Near Top of Bitlines TEM (D) Bitline Plan View TEM (E) Bitlines and Wordlines TEM (F) Bitline and Wordline Layout TEM (F) Wordlines and Device Well TEM (G) Device Well TEM (G)

3.8 Details of Capacitor Cylinders in Oxide Support Layer Level TEM (C) 4.3.9 Capacitor Cylinders Near Top of Bitlines TEM (D) 4.3.10 Bitline Plan View TEM (E) 4.3.11 Bitlines and Wordlines TEM (F) 4.

7 Overview List of Tables 1 Overview Device Summary Process Summary 2 Device Overview Package, Die, and Bond Pad Sizes 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Peripheral Transistor Horizontal Dimensions Peripheral Transistor and Polycide Vertical Dimensions Wordline Transistor Horizontal Dimensions Wordline Transistor Vertical Dimensions STI Measured Dimensions Die Thickness and Well Depths 4 SDRAM Cell Analysis SDRAM Cell Horizontal Dimensions SDRAM Cell Vertical Dimensions 5 Critical Dimensions Package, Die, and Bond Pad Sizes Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Peripheral Transistor Horizontal Dimensions Wordline Transistor Horizontal Dimensions SDRAM Cell Horizontal Dimensions STI Measured Horizontal Dimensions Dielectric Thicknesses Metallization Vertical Dimensions Peripheral Transistor and Polycide Vertical Dimensions Wordline Transistor Vertical Dimensions SDRAM Cell Vertical Dimensions STI Measured Vertical Dimensions Die Thickness and Well Depths

1 Wordline Transistor Horizontal Dimensions 3.7.2 Wordline Transistor Vertical Dimensions 3.8.1 STI Measured Dimensions 3.9.1 Die Thickness and Well Depths 4 SDRAM Cell Analysis 4.1.1 SDRAM Cell Horizontal Dimensions 4.

Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

August 17, 2006 Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor